// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other 
// applicable license agreement, including, without limitation, 
// that your use is for the sole purpose of programming logic 
// devices manufactured by Intel and sold by Intel or its 
// authorized distributors.  Please refer to the applicable 
// agreement for further details.


// 
// Device: Altera EP4CE22F17C6 Package FBGA256
// 

//
// This file contains Slow Corner delays for the design using part EP4CE22F17C6,
// with speed grade 6, core voltage 1.2VmV, and temperature 0 Celsius
//

// 
// This SDF file should be used for ModelSim-Altera (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "DE0_NANO")
  (DATE "08/09/2018 00:24:51")
  (VENDOR "Altera")
  (PROGRAM "Quartus Prime")
  (VERSION "Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[0\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1159:1159:1159) (1154:1154:1154))
        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[1\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1159:1159:1159) (1154:1154:1154))
        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[5\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2737:2737:2737) (2697:2697:2697))
        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[7\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2182:2182:2182) (2178:2178:2178))
        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[9\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2766:2766:2766) (2771:2771:2771))
        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[11\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1982:1982:1982) (1961:1961:1961))
        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[13\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2310:2310:2310) (2266:2266:2266))
        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[15\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1858:1858:1858) (1880:1880:1880))
        (IOPATH i o (4033:4033:4033) (3610:3610:3610))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[17\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2227:2227:2227) (2294:2294:2294))
        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[19\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1510:1510:1510) (1508:1508:1508))
        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[21\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1753:1753:1753) (1731:1731:1731))
        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[23\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1437:1437:1437) (1419:1419:1419))
        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE CLOCK_50\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (459:459:459) (708:708:708))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_pll")
    (INSTANCE PLL_inst\|altpll_component\|auto_generated\|pll1)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (1683:1683:1683) (1683:1683:1683))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE PLL_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (1690:1690:1690) (1671:1671:1671))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE PLL_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (1690:1690:1690) (1671:1671:1671))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[0\]\~10)
    (DELAY
      (ABSOLUTE
        (PORT dataa (257:257:257) (341:341:341))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[1\]\~12)
    (DELAY
      (ABSOLUTE
        (PORT datab (260:260:260) (337:337:337))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[2\]\~14)
    (DELAY
      (ABSOLUTE
        (PORT datab (267:267:267) (344:344:344))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[0\]\~10)
    (DELAY
      (ABSOLUTE
        (PORT datab (246:246:246) (318:318:318))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (635:635:635) (695:695:695))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[1\]\~12)
    (DELAY
      (ABSOLUTE
        (PORT dataa (249:249:249) (325:325:325))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (635:635:635) (695:695:695))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[2\]\~14)
    (DELAY
      (ABSOLUTE
        (PORT dataa (248:248:248) (324:324:324))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (635:635:635) (695:695:695))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[3\]\~16)
    (DELAY
      (ABSOLUTE
        (PORT datab (247:247:247) (320:320:320))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (635:635:635) (695:695:695))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[4\]\~18)
    (DELAY
      (ABSOLUTE
        (PORT dataa (381:381:381) (437:437:437))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (635:635:635) (695:695:695))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[5\]\~20)
    (DELAY
      (ABSOLUTE
        (PORT datab (252:252:252) (330:330:330))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (635:635:635) (695:695:695))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[6\]\~22)
    (DELAY
      (ABSOLUTE
        (PORT datab (254:254:254) (327:327:327))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (635:635:635) (695:695:695))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[7\]\~24)
    (DELAY
      (ABSOLUTE
        (PORT dataa (271:271:271) (350:350:350))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (635:635:635) (695:695:695))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[8\]\~26)
    (DELAY
      (ABSOLUTE
        (PORT dataa (385:385:385) (442:442:442))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (635:635:635) (695:695:695))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[9\]\~28)
    (DELAY
      (ABSOLUTE
        (PORT dataa (254:254:254) (331:331:331))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH cin combout (408:408:408) (387:387:387))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1369:1369:1369))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (635:635:635) (695:695:695))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|Equal0\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (388:388:388) (444:444:444))
        (PORT datab (245:245:245) (318:318:318))
        (PORT datac (227:227:227) (302:302:302))
        (PORT datad (223:223:223) (284:284:284))
        (IOPATH dataa combout (267:267:267) (269:269:269))
        (IOPATH datab combout (265:265:265) (275:275:275))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|Equal0\~2)
    (DELAY
      (ABSOLUTE
        (PORT datac (220:220:220) (292:292:292))
        (PORT datad (225:225:225) (287:287:287))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|Equal0\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (383:383:383) (438:438:438))
        (PORT datab (251:251:251) (328:328:328))
        (PORT datac (244:244:244) (320:320:320))
        (PORT datad (228:228:228) (292:292:292))
        (IOPATH dataa combout (309:309:309) (326:326:326))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE KEY\[0\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (461:461:461) (708:708:708))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[9\]\~17)
    (DELAY
      (ABSOLUTE
        (PORT dataa (186:186:186) (224:224:224))
        (PORT datab (182:182:182) (215:215:215))
        (PORT datac (159:159:159) (190:190:190))
        (PORT datad (2940:2940:2940) (3140:3140:3140))
        (IOPATH dataa combout (265:265:265) (273:273:273))
        (IOPATH datab combout (265:265:265) (275:275:275))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1046:1046:1046) (1092:1092:1092))
        (PORT ena (1316:1316:1316) (1280:1280:1280))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[3\]\~18)
    (DELAY
      (ABSOLUTE
        (PORT datab (263:263:263) (350:350:350))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1046:1046:1046) (1092:1092:1092))
        (PORT ena (1316:1316:1316) (1280:1280:1280))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[4\]\~20)
    (DELAY
      (ABSOLUTE
        (PORT datab (241:241:241) (310:310:310))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1046:1046:1046) (1092:1092:1092))
        (PORT ena (1316:1316:1316) (1280:1280:1280))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[5\]\~22)
    (DELAY
      (ABSOLUTE
        (PORT dataa (242:242:242) (314:314:314))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1046:1046:1046) (1092:1092:1092))
        (PORT ena (1316:1316:1316) (1280:1280:1280))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[6\]\~24)
    (DELAY
      (ABSOLUTE
        (PORT datab (240:240:240) (309:309:309))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1046:1046:1046) (1092:1092:1092))
        (PORT ena (1316:1316:1316) (1280:1280:1280))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[7\]\~26)
    (DELAY
      (ABSOLUTE
        (PORT dataa (241:241:241) (313:313:313))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1046:1046:1046) (1092:1092:1092))
        (PORT ena (1316:1316:1316) (1280:1280:1280))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[8\]\~28)
    (DELAY
      (ABSOLUTE
        (PORT datab (246:246:246) (316:316:316))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1046:1046:1046) (1092:1092:1092))
        (PORT ena (1316:1316:1316) (1280:1280:1280))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[9\]\~30)
    (DELAY
      (ABSOLUTE
        (PORT dataa (248:248:248) (323:323:323))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH cin combout (408:408:408) (387:387:387))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1046:1046:1046) (1092:1092:1092))
        (PORT ena (1316:1316:1316) (1280:1280:1280))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|_\~1)
    (DELAY
      (ABSOLUTE
        (PORT datac (575:575:575) (600:600:600))
        (PORT datad (566:566:566) (589:589:589))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|Equal1\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (644:644:644) (663:663:663))
        (PORT datac (575:575:575) (597:597:597))
        (PORT datad (558:558:558) (575:575:575))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|Equal1\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (595:595:595) (639:639:639))
        (PORT datab (595:595:595) (623:623:623))
        (PORT datac (573:573:573) (601:601:601))
        (PORT datad (165:165:165) (191:191:191))
        (IOPATH dataa combout (265:265:265) (273:273:273))
        (IOPATH datab combout (265:265:265) (275:275:275))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|_\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (597:597:597) (633:633:633))
        (PORT datad (556:556:556) (577:577:577))
        (IOPATH dataa combout (287:287:287) (289:289:289))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[9\]\~16)
    (DELAY
      (ABSOLUTE
        (PORT dataa (326:326:326) (343:343:343))
        (PORT datab (183:183:183) (216:216:216))
        (PORT datac (157:157:157) (189:189:189))
        (PORT datad (3105:3105:3105) (3363:3363:3363))
        (IOPATH dataa combout (273:273:273) (269:269:269))
        (IOPATH datab combout (295:295:295) (294:294:294))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1046:1046:1046) (1092:1092:1092))
        (PORT ena (1316:1316:1316) (1280:1280:1280))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1046:1046:1046) (1092:1092:1092))
        (PORT ena (1316:1316:1316) (1280:1280:1280))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|V_SYNC_NEG\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (593:593:593) (632:632:632))
        (PORT datab (601:601:601) (626:626:626))
        (PORT datac (573:573:573) (603:603:603))
        (PORT datad (558:558:558) (579:579:579))
        (IOPATH dataa combout (287:287:287) (289:289:289))
        (IOPATH datab combout (295:295:295) (294:294:294))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|V_SYNC_NEG\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (593:593:593) (636:636:636))
        (PORT datab (646:646:646) (666:666:666))
        (PORT datac (576:576:576) (599:599:599))
        (PORT datad (554:554:554) (577:577:577))
        (IOPATH dataa combout (299:299:299) (304:304:304))
        (IOPATH datab combout (295:295:295) (300:300:300))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|V_SYNC_NEG\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (184:184:184) (221:221:221))
        (PORT datab (182:182:182) (214:214:214))
        (PORT datac (573:573:573) (598:598:598))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH datab combout (319:319:319) (307:307:307))
        (IOPATH datac combout (220:220:220) (216:216:216))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|H_SYNC_NEG\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (381:381:381) (437:437:437))
        (PORT datab (252:252:252) (330:330:330))
        (PORT datac (246:246:246) (322:322:322))
        (PORT datad (230:230:230) (295:295:295))
        (IOPATH dataa combout (299:299:299) (304:304:304))
        (IOPATH datab combout (300:300:300) (312:312:312))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|H_SYNC_NEG\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (387:387:387) (446:446:446))
        (PORT datab (180:180:180) (212:212:212))
        (PORT datac (228:228:228) (304:304:304))
        (IOPATH dataa combout (307:307:307) (280:280:280))
        (IOPATH datab combout (308:308:308) (281:281:281))
        (IOPATH datac combout (218:218:218) (215:215:215))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[9\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (591:591:591) (628:628:628))
        (PORT datab (439:439:439) (483:483:483))
        (PORT datac (580:580:580) (610:610:610))
        (PORT datad (415:415:415) (464:464:464))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[8\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (593:593:593) (630:630:630))
        (PORT datab (442:442:442) (485:485:485))
        (PORT datac (581:581:581) (611:611:611))
        (PORT datad (418:418:418) (464:464:464))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[7\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (589:589:589) (623:623:623))
        (PORT datab (437:437:437) (479:479:479))
        (PORT datac (581:581:581) (609:609:609))
        (PORT datad (414:414:414) (458:458:458))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|_\~2)
    (DELAY
      (ABSOLUTE
        (PORT datab (264:264:264) (351:351:351))
        (PORT datad (243:243:243) (309:309:309))
        (IOPATH datab combout (275:275:275) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[10\]\~4)
    (DELAY
      (ABSOLUTE
        (PORT datab (264:264:264) (350:350:350))
        (PORT datac (232:232:232) (307:307:307))
        (PORT datad (242:242:242) (310:310:310))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[6\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (589:589:589) (623:623:623))
        (PORT datab (451:451:451) (494:494:494))
        (PORT datac (581:581:581) (609:609:609))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datac combout (220:220:220) (216:216:216))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[5\]\~5)
    (DELAY
      (ABSOLUTE
        (PORT datac (581:581:581) (608:608:608))
        (PORT datad (414:414:414) (461:461:461))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[9\]\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (254:254:254) (334:334:334))
        (PORT datab (262:262:262) (349:349:349))
        (PORT datac (230:230:230) (305:305:305))
        (PORT datad (241:241:241) (310:310:310))
        (IOPATH dataa combout (307:307:307) (323:323:323))
        (IOPATH datab combout (308:308:308) (324:324:324))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[8\]\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (254:254:254) (334:334:334))
        (PORT datab (263:263:263) (348:348:348))
        (PORT datac (230:230:230) (305:305:305))
        (PORT datad (241:241:241) (309:309:309))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH datab combout (319:319:319) (312:312:312))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (321:321:321) (337:337:337))
        (PORT datab (593:593:593) (610:610:610))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (183:183:183) (219:219:219))
        (PORT datab (483:483:483) (476:476:476))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (322:322:322) (338:338:338))
        (PORT datab (182:182:182) (215:215:215))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (319:319:319) (307:307:307))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (184:184:184) (220:220:220))
        (PORT datab (354:354:354) (355:355:355))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~8)
    (DELAY
      (ABSOLUTE
        (PORT datab (181:181:181) (214:214:214))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~10)
    (DELAY
      (ABSOLUTE
        (PORT datab (182:182:182) (215:215:215))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[2\]\[5\]\~8)
    (DELAY
      (ABSOLUTE
        (PORT datac (220:220:220) (292:292:292))
        (PORT datad (222:222:222) (284:284:284))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (599:599:599) (610:610:610))
        (PORT datab (323:323:323) (336:336:336))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (523:523:523) (509:509:509))
        (PORT datab (490:490:490) (472:472:472))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[7\]\~9)
    (DELAY
      (ABSOLUTE
        (PORT dataa (594:594:594) (633:633:633))
        (PORT datab (623:623:623) (639:639:639))
        (PORT datac (565:565:565) (593:593:593))
        (PORT datad (554:554:554) (574:574:574))
        (IOPATH dataa combout (299:299:299) (306:306:306))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[6\]\~10)
    (DELAY
      (ABSOLUTE
        (PORT dataa (597:597:597) (629:629:629))
        (PORT datac (565:565:565) (591:591:591))
        (PORT datad (553:553:553) (574:574:574))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[5\]\~11)
    (DELAY
      (ABSOLUTE
        (PORT datac (566:566:566) (592:592:592))
        (PORT datad (573:573:573) (592:592:592))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (640:640:640) (685:685:685))
        (PORT datab (601:601:601) (619:619:619))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (346:346:346) (350:350:350))
        (PORT datab (658:658:658) (700:700:700))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (636:636:636) (689:689:689))
        (PORT datab (317:317:317) (323:323:323))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (319:319:319) (307:307:307))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (347:347:347) (352:352:352))
        (PORT datab (649:649:649) (702:702:702))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~8)
    (DELAY
      (ABSOLUTE
        (PORT dataa (324:324:324) (340:340:340))
        (PORT datab (648:648:648) (696:696:696))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (319:319:319) (307:307:307))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~10)
    (DELAY
      (ABSOLUTE
        (PORT dataa (361:361:361) (363:363:363))
        (PORT datab (636:636:636) (686:686:686))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~12)
    (DELAY
      (ABSOLUTE
        (PORT dataa (322:322:322) (340:340:340))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~14)
    (DELAY
      (ABSOLUTE
        (PORT datab (353:353:353) (356:356:356))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~16)
    (DELAY
      (ABSOLUTE
        (PORT datab (183:183:183) (217:217:217))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~18)
    (DELAY
      (ABSOLUTE
        (PORT datab (183:183:183) (216:216:216))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|address_reg_b\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1347:1347:1347) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[32\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (461:461:461) (708:708:708))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[33\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (461:461:461) (708:708:708))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pixel_data_RGB332\[0\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datac (220:220:220) (289:289:289))
        (PORT datad (2632:2632:2632) (2818:2818:2818))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE is_lsb\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (179:179:179) (201:201:201))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE is_lsb)
    (DELAY
      (ABSOLUTE
        (PORT clk (1597:1597:1597) (1601:1601:1601))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[0\]\~15)
    (DELAY
      (ABSOLUTE
        (PORT dataa (397:397:397) (437:437:437))
        (PORT datab (923:923:923) (954:954:954))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE last_href\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (2631:2631:2631) (2817:2817:2817))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE last_href)
    (DELAY
      (ABSOLUTE
        (PORT clk (1597:1597:1597) (1601:1601:1601))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[30\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (461:461:461) (708:708:708))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[13\]\~43)
    (DELAY
      (ABSOLUTE
        (PORT datab (248:248:248) (322:322:322))
        (PORT datac (2671:2671:2671) (2865:2865:2865))
        (PORT datad (2627:2627:2627) (2810:2810:2810))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1629:1629:1629))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (3389:3389:3389) (3218:3218:3218))
        (PORT ena (1373:1373:1373) (1345:1345:1345))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[1\]\~17)
    (DELAY
      (ABSOLUTE
        (PORT datab (239:239:239) (307:307:307))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1629:1629:1629))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (3389:3389:3389) (3218:3218:3218))
        (PORT ena (1373:1373:1373) (1345:1345:1345))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[2\]\~19)
    (DELAY
      (ABSOLUTE
        (PORT dataa (240:240:240) (313:313:313))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1629:1629:1629))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (3389:3389:3389) (3218:3218:3218))
        (PORT ena (1373:1373:1373) (1345:1345:1345))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[3\]\~21)
    (DELAY
      (ABSOLUTE
        (PORT datab (240:240:240) (308:308:308))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1629:1629:1629))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (3389:3389:3389) (3218:3218:3218))
        (PORT ena (1373:1373:1373) (1345:1345:1345))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[4\]\~23)
    (DELAY
      (ABSOLUTE
        (PORT dataa (241:241:241) (315:315:315))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1629:1629:1629))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (3389:3389:3389) (3218:3218:3218))
        (PORT ena (1373:1373:1373) (1345:1345:1345))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[5\]\~25)
    (DELAY
      (ABSOLUTE
        (PORT dataa (241:241:241) (315:315:315))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1629:1629:1629))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (3389:3389:3389) (3218:3218:3218))
        (PORT ena (1373:1373:1373) (1345:1345:1345))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[6\]\~27)
    (DELAY
      (ABSOLUTE
        (PORT datab (240:240:240) (310:310:310))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1629:1629:1629))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (3389:3389:3389) (3218:3218:3218))
        (PORT ena (1373:1373:1373) (1345:1345:1345))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[7\]\~29)
    (DELAY
      (ABSOLUTE
        (PORT datab (241:241:241) (310:310:310))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1629:1629:1629))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (3389:3389:3389) (3218:3218:3218))
        (PORT ena (1373:1373:1373) (1345:1345:1345))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[8\]\~31)
    (DELAY
      (ABSOLUTE
        (PORT datab (240:240:240) (310:310:310))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1629:1629:1629))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (3389:3389:3389) (3218:3218:3218))
        (PORT ena (1373:1373:1373) (1345:1345:1345))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[9\]\~33)
    (DELAY
      (ABSOLUTE
        (PORT datab (241:241:241) (310:310:310))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1629:1629:1629))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (3389:3389:3389) (3218:3218:3218))
        (PORT ena (1373:1373:1373) (1345:1345:1345))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[10\]\~35)
    (DELAY
      (ABSOLUTE
        (PORT dataa (242:242:242) (314:314:314))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[10\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1629:1629:1629))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (3389:3389:3389) (3218:3218:3218))
        (PORT ena (1373:1373:1373) (1345:1345:1345))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[11\]\~37)
    (DELAY
      (ABSOLUTE
        (PORT datab (240:240:240) (309:309:309))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1629:1629:1629))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (3389:3389:3389) (3218:3218:3218))
        (PORT ena (1373:1373:1373) (1345:1345:1345))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[12\]\~39)
    (DELAY
      (ABSOLUTE
        (PORT dataa (241:241:241) (313:313:313))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[12\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1629:1629:1629))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (3389:3389:3389) (3218:3218:3218))
        (PORT ena (1373:1373:1373) (1345:1345:1345))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[13\]\~41)
    (DELAY
      (ABSOLUTE
        (PORT datab (239:239:239) (308:308:308))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[13\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1629:1629:1629))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (3389:3389:3389) (3218:3218:3218))
        (PORT ena (1373:1373:1373) (1345:1345:1345))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[0\]\~15)
    (DELAY
      (ABSOLUTE
        (PORT dataa (843:843:843) (879:879:879))
        (PORT datab (263:263:263) (339:339:339))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE always0\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (246:246:246) (320:320:320))
        (PORT datac (2670:2670:2670) (2864:2864:2864))
        (PORT datad (2628:2628:2628) (2813:2813:2813))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1567:1567:1567) (1582:1582:1582))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1003:1003:1003) (1042:1042:1042))
        (PORT ena (3426:3426:3426) (3211:3211:3211))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[1\]\~17)
    (DELAY
      (ABSOLUTE
        (PORT datab (269:269:269) (350:350:350))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1567:1567:1567) (1582:1582:1582))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1003:1003:1003) (1042:1042:1042))
        (PORT ena (3426:3426:3426) (3211:3211:3211))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[2\]\~19)
    (DELAY
      (ABSOLUTE
        (PORT dataa (275:275:275) (366:366:366))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1567:1567:1567) (1582:1582:1582))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1003:1003:1003) (1042:1042:1042))
        (PORT ena (3426:3426:3426) (3211:3211:3211))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[3\]\~21)
    (DELAY
      (ABSOLUTE
        (PORT datab (262:262:262) (348:348:348))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1567:1567:1567) (1582:1582:1582))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1003:1003:1003) (1042:1042:1042))
        (PORT ena (3426:3426:3426) (3211:3211:3211))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[4\]\~23)
    (DELAY
      (ABSOLUTE
        (PORT dataa (242:242:242) (316:316:316))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1567:1567:1567) (1582:1582:1582))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1003:1003:1003) (1042:1042:1042))
        (PORT ena (3426:3426:3426) (3211:3211:3211))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[5\]\~25)
    (DELAY
      (ABSOLUTE
        (PORT dataa (242:242:242) (316:316:316))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1567:1567:1567) (1582:1582:1582))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1003:1003:1003) (1042:1042:1042))
        (PORT ena (3426:3426:3426) (3211:3211:3211))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[6\]\~27)
    (DELAY
      (ABSOLUTE
        (PORT datab (241:241:241) (310:310:310))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1567:1567:1567) (1582:1582:1582))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1003:1003:1003) (1042:1042:1042))
        (PORT ena (3426:3426:3426) (3211:3211:3211))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[7\]\~29)
    (DELAY
      (ABSOLUTE
        (PORT datab (241:241:241) (311:311:311))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1567:1567:1567) (1582:1582:1582))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1003:1003:1003) (1042:1042:1042))
        (PORT ena (3426:3426:3426) (3211:3211:3211))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[9\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (656:656:656) (701:701:701))
        (PORT datab (649:649:649) (687:687:687))
        (PORT datac (626:626:626) (660:660:660))
        (PORT datad (650:650:650) (681:681:681))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[8\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (658:658:658) (701:701:701))
        (PORT datab (650:650:650) (686:686:686))
        (PORT datac (630:630:630) (664:664:664))
        (PORT datad (649:649:649) (678:678:678))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH datab combout (319:319:319) (312:312:312))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|_\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (660:660:660) (683:683:683))
        (PORT datac (639:639:639) (669:669:669))
        (IOPATH datab combout (308:308:308) (300:300:300))
        (IOPATH datac combout (220:220:220) (216:216:216))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[7\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (657:657:657) (699:699:699))
        (PORT datab (650:650:650) (686:686:686))
        (PORT datac (626:626:626) (660:660:660))
        (PORT datad (649:649:649) (680:680:680))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[6\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (656:656:656) (700:700:700))
        (PORT datac (621:621:621) (659:659:659))
        (PORT datad (649:649:649) (680:680:680))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[10\]\~4)
    (DELAY
      (ABSOLUTE
        (PORT datab (262:262:262) (347:347:347))
        (PORT datac (243:243:243) (326:326:326))
        (PORT datad (252:252:252) (332:332:332))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[9\]\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (273:273:273) (364:364:364))
        (PORT datab (262:262:262) (345:345:345))
        (PORT datac (239:239:239) (319:319:319))
        (PORT datad (236:236:236) (303:303:303))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[5\]\~5)
    (DELAY
      (ABSOLUTE
        (PORT dataa (669:669:669) (698:698:698))
        (PORT datad (650:650:650) (679:679:679))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[8\]\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (279:279:279) (372:372:372))
        (PORT datab (265:265:265) (351:351:351))
        (PORT datac (245:245:245) (326:326:326))
        (PORT datad (244:244:244) (312:312:312))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH datab combout (319:319:319) (312:312:312))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (696:696:696) (725:725:725))
        (PORT datab (589:589:589) (583:583:583))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (594:594:594) (583:583:583))
        (PORT datab (182:182:182) (214:214:214))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (183:183:183) (220:220:220))
        (PORT datab (593:593:593) (586:586:586))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (319:319:319) (307:307:307))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (591:591:591) (588:588:588))
        (PORT datab (182:182:182) (216:216:216))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~8)
    (DELAY
      (ABSOLUTE
        (PORT datab (183:183:183) (216:216:216))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~10)
    (DELAY
      (ABSOLUTE
        (PORT datab (182:182:182) (214:214:214))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[8\]\~31)
    (DELAY
      (ABSOLUTE
        (PORT datab (241:241:241) (311:311:311))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1567:1567:1567) (1582:1582:1582))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1003:1003:1003) (1042:1042:1042))
        (PORT ena (3426:3426:3426) (3211:3211:3211))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[9\]\~33)
    (DELAY
      (ABSOLUTE
        (PORT datab (241:241:241) (311:311:311))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1567:1567:1567) (1582:1582:1582))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1003:1003:1003) (1042:1042:1042))
        (PORT ena (3426:3426:3426) (3211:3211:3211))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[2\]\[5\])
    (DELAY
      (ABSOLUTE
        (PORT datac (904:904:904) (930:930:930))
        (PORT datad (897:897:897) (928:928:928))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (627:627:627) (673:673:673))
        (PORT datab (180:180:180) (213:213:213))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (182:182:182) (218:218:218))
        (PORT datab (311:311:311) (329:329:329))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[7\]\~8)
    (DELAY
      (ABSOLUTE
        (PORT dataa (279:279:279) (373:373:373))
        (PORT datab (265:265:265) (352:352:352))
        (PORT datac (246:246:246) (327:327:327))
        (PORT datad (244:244:244) (313:313:313))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[6\]\~9)
    (DELAY
      (ABSOLUTE
        (PORT dataa (280:280:280) (373:373:373))
        (PORT datac (247:247:247) (328:328:328))
        (PORT datad (245:245:245) (314:314:314))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[5\]\~10)
    (DELAY
      (ABSOLUTE
        (PORT datac (636:636:636) (668:668:668))
        (PORT datad (622:622:622) (642:642:642))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (674:674:674) (704:704:704))
        (PORT datab (621:621:621) (636:636:636))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (406:406:406) (444:444:444))
        (PORT datab (181:181:181) (213:213:213))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (578:578:578) (582:582:582))
        (PORT datab (592:592:592) (616:616:616))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (319:319:319) (307:307:307))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (380:380:380) (423:423:423))
        (PORT datab (630:630:630) (628:628:628))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~8)
    (DELAY
      (ABSOLUTE
        (PORT dataa (616:616:616) (650:650:650))
        (PORT datab (351:351:351) (355:355:355))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (319:319:319) (307:307:307))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~10)
    (DELAY
      (ABSOLUTE
        (PORT dataa (551:551:551) (533:533:533))
        (PORT datab (401:401:401) (438:438:438))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~12)
    (DELAY
      (ABSOLUTE
        (PORT dataa (620:620:620) (644:644:644))
        (PORT datab (316:316:316) (328:328:328))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (319:319:319) (307:307:307))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~14)
    (DELAY
      (ABSOLUTE
        (PORT dataa (631:631:631) (648:648:648))
        (PORT datab (352:352:352) (353:353:353))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~16)
    (DELAY
      (ABSOLUTE
        (PORT dataa (409:409:409) (447:447:447))
        (PORT datab (524:524:524) (514:514:514))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (319:319:319) (307:307:307))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~18)
    (DELAY
      (ABSOLUTE
        (PORT dataa (587:587:587) (609:609:609))
        (PORT datab (320:320:320) (332:332:332))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[14\]\~44)
    (DELAY
      (ABSOLUTE
        (PORT dataa (241:241:241) (315:315:315))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH cin combout (408:408:408) (387:387:387))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[14\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1629:1629:1629))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (3389:3389:3389) (3218:3218:3218))
        (PORT ena (1373:1373:1373) (1345:1345:1345))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[10\]\~35)
    (DELAY
      (ABSOLUTE
        (PORT dataa (243:243:243) (316:316:316))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH cin combout (408:408:408) (387:387:387))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[10\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1567:1567:1567) (1582:1582:1582))
        (PORT d (67:67:67) (78:78:78))
        (PORT sclr (1003:1003:1003) (1042:1042:1042))
        (PORT ena (3426:3426:3426) (3211:3211:3211))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD sclr (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[2\]\[6\]\~12)
    (DELAY
      (ABSOLUTE
        (PORT datab (932:932:932) (963:963:963))
        (PORT datac (901:901:901) (929:929:929))
        (PORT datad (879:879:879) (905:905:905))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[10\]\~11)
    (DELAY
      (ABSOLUTE
        (PORT dataa (653:653:653) (701:701:701))
        (PORT datac (626:626:626) (664:664:664))
        (PORT datad (622:622:622) (655:655:655))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~12)
    (DELAY
      (ABSOLUTE
        (PORT datad (159:159:159) (180:180:180))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (565:565:565) (576:576:576))
        (PORT datad (158:158:158) (179:179:179))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~20)
    (DELAY
      (ABSOLUTE
        (PORT datab (365:365:365) (411:411:411))
        (PORT datad (490:490:490) (479:479:479))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE W_EN\~0)
    (DELAY
      (ABSOLUTE
        (PORT datac (222:222:222) (292:292:292))
        (PORT datad (2627:2627:2627) (2812:2812:2812))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE W_EN\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (181:181:181) (203:203:203))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE W_EN)
    (DELAY
      (ABSOLUTE
        (PORT clk (1597:1597:1597) (1601:1601:1601))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|decode2\|w_anode300w\[2\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (199:199:199) (244:244:244))
        (PORT datac (173:173:173) (213:213:213))
        (PORT datad (877:877:877) (913:913:913))
        (IOPATH datab combout (295:295:295) (285:285:285))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE PLL_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[2\]\~clkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (1690:1690:1690) (1671:1671:1671))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[10\]\~12)
    (DELAY
      (ABSOLUTE
        (PORT datab (437:437:437) (481:481:481))
        (PORT datac (560:560:560) (594:594:594))
        (PORT datad (414:414:414) (461:461:461))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~12)
    (DELAY
      (ABSOLUTE
        (PORT datad (159:159:159) (181:181:181))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (315:315:315) (335:335:335))
        (PORT datab (354:354:354) (353:353:353))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH cin combout (408:408:408) (387:387:387))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~20)
    (DELAY
      (ABSOLUTE
        (PORT datab (183:183:183) (217:217:217))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH cin combout (408:408:408) (387:387:387))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|rden_decode_b\|w_anode338w\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datac (347:347:347) (366:366:366))
        (PORT datad (344:344:344) (357:357:357))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[27\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (461:461:461) (708:708:708))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pixel_data_RGB332\[7\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (2949:2949:2949) (3136:3136:3136))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1862:1862:1862) (1873:1873:1873))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (1143:1143:1143) (1123:1123:1123))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1610:1610:1610) (1704:1704:1704))
        (PORT clk (1638:1638:1638) (1664:1664:1664))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1806:1806:1806) (1858:1858:1858))
        (PORT d[1] (2449:2449:2449) (2603:2603:2603))
        (PORT d[2] (2792:2792:2792) (2868:2868:2868))
        (PORT d[3] (1185:1185:1185) (1204:1204:1204))
        (PORT d[4] (1579:1579:1579) (1560:1560:1560))
        (PORT d[5] (1030:1030:1030) (1021:1021:1021))
        (PORT d[6] (1457:1457:1457) (1500:1500:1500))
        (PORT d[7] (2469:2469:2469) (2493:2493:2493))
        (PORT d[8] (1273:1273:1273) (1264:1264:1264))
        (PORT d[9] (1296:1296:1296) (1249:1249:1249))
        (PORT d[10] (1334:1334:1334) (1307:1307:1307))
        (PORT d[11] (2930:2930:2930) (2936:2936:2936))
        (PORT d[12] (1812:1812:1812) (1828:1828:1828))
        (PORT clk (1635:1635:1635) (1662:1662:1662))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2300:2300:2300) (2263:2263:2263))
        (PORT clk (1635:1635:1635) (1662:1662:1662))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1664:1664:1664))
        (PORT d[0] (2756:2756:2756) (2729:2729:2729))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1665:1665:1665))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1665:1665:1665))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1665:1665:1665))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1665:1665:1665))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1661:1661:1661) (1707:1707:1707))
        (PORT d[1] (1456:1456:1456) (1520:1520:1520))
        (PORT d[2] (1423:1423:1423) (1477:1477:1477))
        (PORT d[3] (1461:1461:1461) (1516:1516:1516))
        (PORT d[4] (1934:1934:1934) (1937:1937:1937))
        (PORT d[5] (2067:2067:2067) (2043:2043:2043))
        (PORT d[6] (1774:1774:1774) (1761:1761:1761))
        (PORT d[7] (1923:1923:1923) (1973:1973:1973))
        (PORT d[8] (2060:2060:2060) (2055:2055:2055))
        (PORT d[9] (1637:1637:1637) (1630:1630:1630))
        (PORT d[10] (1814:1814:1814) (1826:1826:1826))
        (PORT d[11] (1627:1627:1627) (1618:1618:1618))
        (PORT d[12] (1648:1648:1648) (1668:1668:1668))
        (PORT clk (1602:1602:1602) (1598:1598:1598))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1598:1598:1598))
        (PORT d[0] (1518:1518:1518) (1507:1507:1507))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1599:1599:1599))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1599:1599:1599))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1599:1599:1599))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|decode2\|w_anode313w\[2\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (202:202:202) (248:248:248))
        (PORT datac (177:177:177) (216:216:216))
        (PORT datad (877:877:877) (913:913:913))
        (IOPATH datab combout (273:273:273) (275:275:275))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|rden_decode_b\|w_anode352w\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datac (348:348:348) (366:366:366))
        (PORT datad (344:344:344) (357:357:357))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1362:1362:1362) (1457:1457:1457))
        (PORT clk (1638:1638:1638) (1665:1665:1665))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2122:2122:2122) (2185:2185:2185))
        (PORT d[1] (2443:2443:2443) (2597:2597:2597))
        (PORT d[2] (2792:2792:2792) (2865:2865:2865))
        (PORT d[3] (1214:1214:1214) (1246:1246:1246))
        (PORT d[4] (1300:1300:1300) (1294:1294:1294))
        (PORT d[5] (1072:1072:1072) (1075:1075:1075))
        (PORT d[6] (1186:1186:1186) (1210:1210:1210))
        (PORT d[7] (1354:1354:1354) (1320:1320:1320))
        (PORT d[8] (1052:1052:1052) (1057:1057:1057))
        (PORT d[9] (1793:1793:1793) (1807:1807:1807))
        (PORT d[10] (1095:1095:1095) (1088:1088:1088))
        (PORT d[11] (2608:2608:2608) (2621:2621:2621))
        (PORT d[12] (1804:1804:1804) (1806:1806:1806))
        (PORT clk (1635:1635:1635) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2354:2354:2354) (2305:2305:2305))
        (PORT clk (1635:1635:1635) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1665:1665:1665))
        (PORT d[0] (2810:2810:2810) (2771:2771:2771))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1418:1418:1418) (1466:1466:1466))
        (PORT d[1] (1201:1201:1201) (1263:1263:1263))
        (PORT d[2] (1721:1721:1721) (1797:1797:1797))
        (PORT d[3] (1759:1759:1759) (1829:1829:1829))
        (PORT d[4] (2172:2172:2172) (2185:2185:2185))
        (PORT d[5] (2095:2095:2095) (2087:2087:2087))
        (PORT d[6] (1788:1788:1788) (1791:1791:1791))
        (PORT d[7] (1491:1491:1491) (1491:1491:1491))
        (PORT d[8] (2283:2283:2283) (2305:2305:2305))
        (PORT d[9] (2130:2130:2130) (2140:2140:2140))
        (PORT d[10] (2260:2260:2260) (2236:2236:2236))
        (PORT d[11] (1365:1365:1365) (1379:1379:1379))
        (PORT d[12] (1865:1865:1865) (1902:1902:1902))
        (PORT clk (1602:1602:1602) (1599:1599:1599))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1599:1599:1599))
        (PORT d[0] (1534:1534:1534) (1517:1517:1517))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1600:1600:1600))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1600:1600:1600))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1600:1600:1600))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|address_reg_b\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1347:1347:1347) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[7\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1158:1158:1158) (1222:1222:1222))
        (PORT datab (866:866:866) (893:893:893))
        (PORT datac (1049:1049:1049) (1048:1048:1048))
        (PORT datad (907:907:907) (967:967:967))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH datab combout (319:319:319) (307:307:307))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|decode2\|w_anode321w\[2\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (200:200:200) (243:243:243))
        (PORT datac (174:174:174) (211:211:211))
        (PORT datad (882:882:882) (919:919:919))
        (IOPATH datab combout (295:295:295) (294:294:294))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|rden_decode_b\|w_anode361w\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datac (174:174:174) (205:205:205))
        (PORT datad (177:177:177) (198:198:198))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1378:1378:1378) (1474:1474:1474))
        (PORT clk (1638:1638:1638) (1666:1666:1666))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1527:1527:1527) (1574:1574:1574))
        (PORT d[1] (2175:2175:2175) (2320:2320:2320))
        (PORT d[2] (2761:2761:2761) (2833:2833:2833))
        (PORT d[3] (1245:1245:1245) (1293:1293:1293))
        (PORT d[4] (1320:1320:1320) (1331:1331:1331))
        (PORT d[5] (1087:1087:1087) (1111:1111:1111))
        (PORT d[6] (1208:1208:1208) (1235:1235:1235))
        (PORT d[7] (2188:2188:2188) (2212:2212:2212))
        (PORT d[8] (1088:1088:1088) (1113:1113:1113))
        (PORT d[9] (1815:1815:1815) (1831:1831:1831))
        (PORT d[10] (1106:1106:1106) (1115:1115:1115))
        (PORT d[11] (2624:2624:2624) (2635:2635:2635))
        (PORT d[12] (1570:1570:1570) (1563:1563:1563))
        (PORT clk (1635:1635:1635) (1664:1664:1664))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2005:2005:2005) (2004:2004:2004))
        (PORT clk (1635:1635:1635) (1664:1664:1664))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
        (PORT d[0] (2461:2461:2461) (2470:2470:2470))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1377:1377:1377) (1403:1403:1403))
        (PORT d[1] (1741:1741:1741) (1803:1803:1803))
        (PORT d[2] (1741:1741:1741) (1817:1817:1817))
        (PORT d[3] (1750:1750:1750) (1819:1819:1819))
        (PORT d[4] (2202:2202:2202) (2220:2220:2220))
        (PORT d[5] (2085:2085:2085) (2094:2094:2094))
        (PORT d[6] (1824:1824:1824) (1847:1847:1847))
        (PORT d[7] (1916:1916:1916) (1923:1923:1923))
        (PORT d[8] (2316:2316:2316) (2347:2347:2347))
        (PORT d[9] (1899:1899:1899) (1923:1923:1923))
        (PORT d[10] (2301:2301:2301) (2306:2306:2306))
        (PORT d[11] (1895:1895:1895) (1920:1920:1920))
        (PORT d[12] (1870:1870:1870) (1913:1913:1913))
        (PORT clk (1602:1602:1602) (1600:1600:1600))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1600:1600:1600))
        (PORT d[0] (1217:1217:1217) (1194:1194:1194))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1601:1601:1601))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1601:1601:1601))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1601:1601:1601))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|decode2\|w_anode329w\[2\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (200:200:200) (243:243:243))
        (PORT datac (174:174:174) (211:211:211))
        (PORT datad (882:882:882) (919:919:919))
        (IOPATH datab combout (275:275:275) (275:275:275))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|rden_decode_b\|w_anode370w\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datac (346:346:346) (362:362:362))
        (PORT datad (342:342:342) (353:353:353))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[23\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (461:461:461) (708:708:708))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pixel_data_RGB332\[0\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (2703:2703:2703) (2913:2913:2913))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1827:1827:1827) (1830:1830:1830))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (1179:1179:1179) (1172:1172:1172))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[24\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (461:461:461) (708:708:708))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pixel_data_RGB332\[1\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (2821:2821:2821) (2992:2992:2992))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1827:1827:1827) (1830:1830:1830))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (1179:1179:1179) (1172:1172:1172))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[20\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (461:461:461) (708:708:708))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1862:1862:1862) (1873:1873:1873))
        (PORT asdata (3250:3250:3250) (3448:3448:3448))
        (PORT ena (1143:1143:1143) (1123:1123:1123))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD asdata (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[21\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (461:461:461) (708:708:708))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1862:1862:1862) (1873:1873:1873))
        (PORT asdata (2972:2972:2972) (3171:3171:3171))
        (PORT ena (1143:1143:1143) (1123:1123:1123))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD asdata (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[22\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (459:459:459) (708:708:708))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pixel_data_RGB332\[4\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (2985:2985:2985) (3257:3257:3257))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1862:1862:1862) (1873:1873:1873))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (1143:1143:1143) (1123:1123:1123))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[25\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (459:459:459) (708:708:708))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1862:1862:1862) (1873:1873:1873))
        (PORT asdata (3204:3204:3204) (3444:3444:3444))
        (PORT ena (1143:1143:1143) (1123:1123:1123))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD asdata (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[26\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (461:461:461) (708:708:708))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1862:1862:1862) (1873:1873:1873))
        (PORT asdata (2993:2993:2993) (3178:3178:3178))
        (PORT ena (1143:1143:1143) (1123:1123:1123))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD asdata (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (968:968:968) (993:993:993))
        (PORT d[1] (914:914:914) (943:943:943))
        (PORT d[2] (927:927:927) (951:951:951))
        (PORT d[3] (1176:1176:1176) (1220:1220:1220))
        (PORT d[4] (1204:1204:1204) (1212:1212:1212))
        (PORT d[5] (927:927:927) (955:955:955))
        (PORT d[6] (1204:1204:1204) (1246:1246:1246))
        (PORT d[7] (904:904:904) (932:932:932))
        (PORT clk (1644:1644:1644) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1366:1366:1366) (1401:1401:1401))
        (PORT d[1] (1741:1741:1741) (1799:1799:1799))
        (PORT d[2] (1223:1223:1223) (1266:1266:1266))
        (PORT d[3] (1707:1707:1707) (1755:1755:1755))
        (PORT d[4] (1156:1156:1156) (1188:1188:1188))
        (PORT d[5] (2432:2432:2432) (2507:2507:2507))
        (PORT d[6] (2105:2105:2105) (2176:2176:2176))
        (PORT d[7] (2226:2226:2226) (2275:2275:2275))
        (PORT d[8] (1330:1330:1330) (1328:1328:1328))
        (PORT d[9] (1242:1242:1242) (1266:1266:1266))
        (PORT clk (1641:1641:1641) (1668:1668:1668))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1348:1348:1348) (1297:1297:1297))
        (PORT clk (1641:1641:1641) (1668:1668:1668))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1670:1670:1670))
        (PORT d[0] (1804:1804:1804) (1763:1763:1763))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1671:1671:1671))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1651:1651:1651) (1674:1674:1674))
        (PORT d[1] (1418:1418:1418) (1441:1441:1441))
        (PORT d[2] (1132:1132:1132) (1142:1142:1142))
        (PORT d[3] (1377:1377:1377) (1425:1425:1425))
        (PORT d[4] (1082:1082:1082) (1063:1063:1063))
        (PORT d[5] (2052:2052:2052) (2029:2029:2029))
        (PORT d[6] (2391:2391:2391) (2417:2417:2417))
        (PORT d[7] (1049:1049:1049) (1039:1039:1039))
        (PORT d[8] (2150:2150:2150) (2183:2183:2183))
        (PORT d[9] (1889:1889:1889) (1925:1925:1925))
        (PORT clk (1608:1608:1608) (1604:1604:1604))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1608:1608:1608) (1604:1604:1604))
        (PORT d[0] (724:724:724) (664:664:664))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1609:1609:1609) (1605:1605:1605))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1609:1609:1609) (1605:1605:1605))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1609:1609:1609) (1605:1605:1605))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[7\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1161:1161:1161) (1229:1229:1229))
        (PORT datab (940:940:940) (996:996:996))
        (PORT datac (763:763:763) (753:753:753))
        (PORT datad (1028:1028:1028) (994:994:994))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH datab combout (308:308:308) (281:281:281))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[7\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (647:647:647) (699:699:699))
        (PORT datac (573:573:573) (598:598:598))
        (PORT datad (560:560:560) (587:587:587))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE LessThan0\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (635:635:635) (686:686:686))
        (PORT datab (657:657:657) (700:700:700))
        (PORT datac (602:602:602) (650:650:650))
        (PORT datad (621:621:621) (667:667:667))
        (IOPATH dataa combout (273:273:273) (269:269:269))
        (IOPATH datab combout (275:275:275) (275:275:275))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[7\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (184:184:184) (221:221:221))
        (PORT datab (190:190:190) (225:225:225))
        (PORT datac (575:575:575) (604:604:604))
        (PORT datad (300:300:300) (298:298:298))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH datab combout (295:295:295) (300:300:300))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[7\]\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1093:1093:1093) (1123:1123:1123))
        (PORT datab (182:182:182) (214:214:214))
        (PORT datac (155:155:155) (185:185:185))
        (PORT datad (1025:1025:1025) (1010:1010:1010))
        (IOPATH dataa combout (287:287:287) (289:289:289))
        (IOPATH datab combout (273:273:273) (275:275:275))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1889:1889:1889) (1915:1915:1915))
        (PORT clk (1637:1637:1637) (1665:1665:1665))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1835:1835:1835) (1879:1879:1879))
        (PORT d[1] (2167:2167:2167) (2307:2307:2307))
        (PORT d[2] (2470:2470:2470) (2528:2528:2528))
        (PORT d[3] (1496:1496:1496) (1545:1545:1545))
        (PORT d[4] (1592:1592:1592) (1598:1598:1598))
        (PORT d[5] (1355:1355:1355) (1387:1387:1387))
        (PORT d[6] (1857:1857:1857) (1933:1933:1933))
        (PORT d[7] (1897:1897:1897) (1914:1914:1914))
        (PORT d[8] (1333:1333:1333) (1356:1356:1356))
        (PORT d[9] (1719:1719:1719) (1688:1688:1688))
        (PORT d[10] (1372:1372:1372) (1391:1391:1391))
        (PORT d[11] (2313:2313:2313) (2308:2308:2308))
        (PORT d[12] (2107:2107:2107) (2193:2193:2193))
        (PORT clk (1634:1634:1634) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2028:2028:2028) (1952:1952:1952))
        (PORT clk (1634:1634:1634) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1637:1637:1637) (1665:1665:1665))
        (PORT d[0] (2484:2484:2484) (2422:2422:2422))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1994:1994:1994) (2045:2045:2045))
        (PORT d[1] (1510:1510:1510) (1589:1589:1589))
        (PORT d[2] (2012:2012:2012) (2090:2090:2090))
        (PORT d[3] (2019:2019:2019) (2099:2099:2099))
        (PORT d[4] (2452:2452:2452) (2478:2478:2478))
        (PORT d[5] (2367:2367:2367) (2368:2368:2368))
        (PORT d[6] (2123:2123:2123) (2162:2162:2162))
        (PORT d[7] (1216:1216:1216) (1191:1191:1191))
        (PORT d[8] (2625:2625:2625) (2668:2668:2668))
        (PORT d[9] (2205:2205:2205) (2239:2239:2239))
        (PORT d[10] (2532:2532:2532) (2525:2525:2525))
        (PORT d[11] (2187:2187:2187) (2218:2218:2218))
        (PORT d[12] (1125:1125:1125) (1127:1127:1127))
        (PORT clk (1601:1601:1601) (1599:1599:1599))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1601:1601:1601) (1599:1599:1599))
        (PORT d[0] (1812:1812:1812) (1811:1811:1811))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1600:1600:1600))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1600:1600:1600))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1600:1600:1600))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2137:2137:2137) (2152:2152:2152))
        (PORT clk (1636:1636:1636) (1662:1662:1662))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1831:1831:1831) (1888:1888:1888))
        (PORT d[1] (1910:1910:1910) (2049:2049:2049))
        (PORT d[2] (2466:2466:2466) (2528:2528:2528))
        (PORT d[3] (1525:1525:1525) (1586:1586:1586))
        (PORT d[4] (1599:1599:1599) (1620:1620:1620))
        (PORT d[5] (1330:1330:1330) (1360:1360:1360))
        (PORT d[6] (2299:2299:2299) (2413:2413:2413))
        (PORT d[7] (1912:1912:1912) (1928:1928:1928))
        (PORT d[8] (1387:1387:1387) (1425:1425:1425))
        (PORT d[9] (1767:1767:1767) (1758:1758:1758))
        (PORT d[10] (1375:1375:1375) (1396:1396:1396))
        (PORT d[11] (2333:2333:2333) (2328:2328:2328))
        (PORT d[12] (2153:2153:2153) (2241:2241:2241))
        (PORT clk (1633:1633:1633) (1660:1660:1660))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1987:1987:1987) (1961:1961:1961))
        (PORT clk (1633:1633:1633) (1660:1660:1660))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1662:1662:1662))
        (PORT d[0] (2443:2443:2443) (2427:2427:2427))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1637:1637:1637) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1637:1637:1637) (1663:1663:1663))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1637:1637:1637) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1637:1637:1637) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1707:1707:1707) (1748:1748:1748))
        (PORT d[1] (2015:2015:2015) (2082:2082:2082))
        (PORT d[2] (1992:1992:1992) (2075:2075:2075))
        (PORT d[3] (1783:1783:1783) (1824:1824:1824))
        (PORT d[4] (2479:2479:2479) (2507:2507:2507))
        (PORT d[5] (2354:2354:2354) (2367:2367:2367))
        (PORT d[6] (2082:2082:2082) (2103:2103:2103))
        (PORT d[7] (1746:1746:1746) (1700:1700:1700))
        (PORT d[8] (2601:2601:2601) (2641:2641:2641))
        (PORT d[9] (2210:2210:2210) (2247:2247:2247))
        (PORT d[10] (2537:2537:2537) (2532:2532:2532))
        (PORT d[11] (2176:2176:2176) (2210:2210:2210))
        (PORT d[12] (1147:1147:1147) (1149:1149:1149))
        (PORT clk (1600:1600:1600) (1596:1596:1596))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1600:1600:1600) (1596:1596:1596))
        (PORT d[0] (959:959:959) (925:925:925))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1601:1601:1601) (1597:1597:1597))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1601:1601:1601) (1597:1597:1597))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1601:1601:1601) (1597:1597:1597))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[6\]\~5)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1154:1154:1154) (1220:1220:1220))
        (PORT datab (625:625:625) (611:611:611))
        (PORT datac (845:845:845) (815:815:815))
        (PORT datad (908:908:908) (968:968:968))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1392:1392:1392) (1424:1424:1424))
        (PORT clk (1630:1630:1630) (1658:1658:1658))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2092:2092:2092) (2136:2136:2136))
        (PORT d[1] (2112:2112:2112) (2224:2224:2224))
        (PORT d[2] (2191:2191:2191) (2227:2227:2227))
        (PORT d[3] (1761:1761:1761) (1817:1817:1817))
        (PORT d[4] (1850:1850:1850) (1856:1856:1856))
        (PORT d[5] (1669:1669:1669) (1702:1702:1702))
        (PORT d[6] (2063:2063:2063) (2163:2163:2163))
        (PORT d[7] (1896:1896:1896) (1887:1887:1887))
        (PORT d[8] (1595:1595:1595) (1617:1617:1617))
        (PORT d[9] (1778:1778:1778) (1772:1772:1772))
        (PORT d[10] (1646:1646:1646) (1673:1673:1673))
        (PORT d[11] (1570:1570:1570) (1571:1571:1571))
        (PORT d[12] (1879:1879:1879) (1958:1958:1958))
        (PORT clk (1627:1627:1627) (1656:1656:1656))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1758:1758:1758) (1785:1785:1785))
        (PORT clk (1627:1627:1627) (1656:1656:1656))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1630:1630:1630) (1658:1658:1658))
        (PORT d[0] (2214:2214:2214) (2250:2250:2250))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1631:1631:1631) (1659:1659:1659))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1631:1631:1631) (1659:1659:1659))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1631:1631:1631) (1659:1659:1659))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1631:1631:1631) (1659:1659:1659))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1661:1661:1661) (1692:1692:1692))
        (PORT d[1] (1205:1205:1205) (1259:1259:1259))
        (PORT d[2] (1932:1932:1932) (1947:1947:1947))
        (PORT d[3] (1228:1228:1228) (1294:1294:1294))
        (PORT d[4] (2724:2724:2724) (2759:2759:2759))
        (PORT d[5] (2917:2917:2917) (2938:2938:2938))
        (PORT d[6] (2402:2402:2402) (2443:2443:2443))
        (PORT d[7] (1089:1089:1089) (1070:1070:1070))
        (PORT d[8] (2903:2903:2903) (2955:2955:2955))
        (PORT d[9] (2515:2515:2515) (2565:2565:2565))
        (PORT d[10] (2801:2801:2801) (2798:2798:2798))
        (PORT d[11] (2422:2422:2422) (2461:2461:2461))
        (PORT d[12] (1102:1102:1102) (1084:1084:1084))
        (PORT clk (1594:1594:1594) (1592:1592:1592))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1594:1594:1594) (1592:1592:1592))
        (PORT d[0] (720:720:720) (682:682:682))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1595:1595:1595) (1593:1593:1593))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1595:1595:1595) (1593:1593:1593))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1595:1595:1595) (1593:1593:1593))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[6\]\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1160:1160:1160) (1226:1226:1226))
        (PORT datab (940:940:940) (996:996:996))
        (PORT datac (572:572:572) (570:570:570))
        (PORT datad (990:990:990) (949:949:949))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH datab combout (308:308:308) (281:281:281))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[6\]\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (183:183:183) (220:220:220))
        (PORT datab (183:183:183) (217:217:217))
        (PORT datac (1065:1065:1065) (1096:1096:1096))
        (PORT datad (1024:1024:1024) (1012:1012:1012))
        (IOPATH dataa combout (272:272:272) (269:269:269))
        (IOPATH datab combout (273:273:273) (275:275:275))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1445:1445:1445) (1482:1482:1482))
        (PORT clk (1638:1638:1638) (1666:1666:1666))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1796:1796:1796) (1840:1840:1840))
        (PORT d[1] (2172:2172:2172) (2313:2313:2313))
        (PORT d[2] (2512:2512:2512) (2577:2577:2577))
        (PORT d[3] (1208:1208:1208) (1255:1255:1255))
        (PORT d[4] (1322:1322:1322) (1325:1325:1325))
        (PORT d[5] (1092:1092:1092) (1118:1118:1118))
        (PORT d[6] (1887:1887:1887) (1959:1959:1959))
        (PORT d[7] (1335:1335:1335) (1322:1322:1322))
        (PORT d[8] (1094:1094:1094) (1120:1120:1120))
        (PORT d[9] (1788:1788:1788) (1796:1796:1796))
        (PORT d[10] (1111:1111:1111) (1124:1124:1124))
        (PORT d[11] (2570:2570:2570) (2556:2556:2556))
        (PORT d[12] (1071:1071:1071) (1082:1082:1082))
        (PORT clk (1635:1635:1635) (1664:1664:1664))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2008:2008:2008) (1967:1967:1967))
        (PORT clk (1635:1635:1635) (1664:1664:1664))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
        (PORT d[0] (2464:2464:2464) (2433:2433:2433))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2006:2006:2006) (2056:2056:2056))
        (PORT d[1] (1503:1503:1503) (1579:1579:1579))
        (PORT d[2] (1717:1717:1717) (1794:1794:1794))
        (PORT d[3] (2029:2029:2029) (2092:2092:2092))
        (PORT d[4] (2202:2202:2202) (2222:2222:2222))
        (PORT d[5] (2113:2113:2113) (2126:2126:2126))
        (PORT d[6] (1829:1829:1829) (1855:1855:1855))
        (PORT d[7] (1496:1496:1496) (1485:1485:1485))
        (PORT d[8] (2313:2313:2313) (2341:2341:2341))
        (PORT d[9] (1904:1904:1904) (1930:1930:1930))
        (PORT d[10] (2319:2319:2319) (2333:2333:2333))
        (PORT d[11] (1875:1875:1875) (1899:1899:1899))
        (PORT d[12] (2120:2120:2120) (2150:2150:2150))
        (PORT clk (1602:1602:1602) (1600:1600:1600))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1600:1600:1600))
        (PORT d[0] (1210:1210:1210) (1181:1181:1181))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1601:1601:1601))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1601:1601:1601))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1601:1601:1601))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1718:1718:1718) (1740:1740:1740))
        (PORT clk (1638:1638:1638) (1666:1666:1666))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1819:1819:1819) (1871:1871:1871))
        (PORT d[1] (2151:2151:2151) (2297:2297:2297))
        (PORT d[2] (2470:2470:2470) (2529:2529:2529))
        (PORT d[3] (1464:1464:1464) (1502:1502:1502))
        (PORT d[4] (1349:1349:1349) (1361:1361:1361))
        (PORT d[5] (1068:1068:1068) (1091:1091:1091))
        (PORT d[6] (1886:1886:1886) (1958:1958:1958))
        (PORT d[7] (1897:1897:1897) (1915:1915:1915))
        (PORT d[8] (1069:1069:1069) (1092:1092:1092))
        (PORT d[9] (1781:1781:1781) (1775:1775:1775))
        (PORT d[10] (1112:1112:1112) (1125:1125:1125))
        (PORT d[11] (2339:2339:2339) (2338:2338:2338))
        (PORT d[12] (1418:1418:1418) (1439:1439:1439))
        (PORT clk (1635:1635:1635) (1664:1664:1664))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2058:2058:2058) (1999:1999:1999))
        (PORT clk (1635:1635:1635) (1664:1664:1664))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
        (PORT d[0] (2514:2514:2514) (2465:2465:2465))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2005:2005:2005) (2055:2055:2055))
        (PORT d[1] (1517:1517:1517) (1587:1587:1587))
        (PORT d[2] (2007:2007:2007) (2090:2090:2090))
        (PORT d[3] (2059:2059:2059) (2131:2131:2131))
        (PORT d[4] (1914:1914:1914) (1940:1940:1940))
        (PORT d[5] (2114:2114:2114) (2127:2127:2127))
        (PORT d[6] (2088:2088:2088) (2113:2113:2113))
        (PORT d[7] (1118:1118:1118) (1110:1110:1110))
        (PORT d[8] (2587:2587:2587) (2626:2626:2626))
        (PORT d[9] (2171:2171:2171) (2204:2204:2204))
        (PORT d[10] (2549:2549:2549) (2535:2535:2535))
        (PORT d[11] (2161:2161:2161) (2184:2184:2184))
        (PORT d[12] (2127:2127:2127) (2170:2170:2170))
        (PORT clk (1602:1602:1602) (1600:1600:1600))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1600:1600:1600))
        (PORT d[0] (1528:1528:1528) (1527:1527:1527))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1601:1601:1601))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1601:1601:1601))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1601:1601:1601))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[5\]\~8)
    (DELAY
      (ABSOLUTE
        (PORT dataa (623:623:623) (637:637:637))
        (PORT datab (944:944:944) (1003:1003:1003))
        (PORT datac (760:760:760) (735:735:735))
        (PORT datad (1134:1134:1134) (1187:1187:1187))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (924:924:924) (959:959:959))
        (PORT clk (1634:1634:1634) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1656:1656:1656) (1700:1700:1700))
        (PORT d[1] (1748:1748:1748) (1813:1813:1813))
        (PORT d[2] (1486:1486:1486) (1530:1530:1530))
        (PORT d[3] (1506:1506:1506) (1572:1572:1572))
        (PORT d[4] (1408:1408:1408) (1442:1442:1442))
        (PORT d[5] (2231:2231:2231) (2299:2299:2299))
        (PORT d[6] (2314:2314:2314) (2395:2395:2395))
        (PORT d[7] (2402:2402:2402) (2419:2419:2419))
        (PORT d[8] (1829:1829:1829) (1822:1822:1822))
        (PORT d[9] (1825:1825:1825) (1846:1846:1846))
        (PORT d[10] (1405:1405:1405) (1427:1427:1427))
        (PORT d[11] (1617:1617:1617) (1619:1619:1619))
        (PORT d[12] (2403:2403:2403) (2474:2474:2474))
        (PORT clk (1631:1631:1631) (1661:1661:1661))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1692:1692:1692) (1668:1668:1668))
        (PORT clk (1631:1631:1631) (1661:1661:1661))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1634:1634:1634) (1663:1663:1663))
        (PORT d[0] (2148:2148:2148) (2134:2134:2134))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1664:1664:1664))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1664:1664:1664))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1664:1664:1664))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1664:1664:1664))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1385:1385:1385) (1403:1403:1403))
        (PORT d[1] (1422:1422:1422) (1430:1430:1430))
        (PORT d[2] (1457:1457:1457) (1479:1479:1479))
        (PORT d[3] (1400:1400:1400) (1425:1425:1425))
        (PORT d[4] (818:818:818) (808:808:808))
        (PORT d[5] (2547:2547:2547) (2527:2527:2527))
        (PORT d[6] (2651:2651:2651) (2680:2680:2680))
        (PORT d[7] (1106:1106:1106) (1083:1083:1083))
        (PORT d[8] (1073:1073:1073) (1066:1066:1066))
        (PORT d[9] (2142:2142:2142) (2172:2172:2172))
        (PORT d[10] (1599:1599:1599) (1598:1598:1598))
        (PORT d[11] (2621:2621:2621) (2656:2656:2656))
        (PORT d[12] (2142:2142:2142) (2184:2184:2184))
        (PORT clk (1598:1598:1598) (1597:1597:1597))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1598:1598:1598) (1597:1597:1597))
        (PORT d[0] (1179:1179:1179) (1102:1102:1102))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1599:1599:1599) (1598:1598:1598))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1599:1599:1599) (1598:1598:1598))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1599:1599:1599) (1598:1598:1598))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[5\]\~9)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1160:1160:1160) (1226:1226:1226))
        (PORT datab (940:940:940) (998:998:998))
        (PORT datac (1286:1286:1286) (1263:1263:1263))
        (PORT datad (1003:1003:1003) (965:965:965))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH datab combout (308:308:308) (281:281:281))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[5\]\~10)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1096:1096:1096) (1125:1125:1125))
        (PORT datab (183:183:183) (215:215:215))
        (PORT datac (157:157:157) (187:187:187))
        (PORT datad (1024:1024:1024) (1010:1010:1010))
        (IOPATH dataa combout (287:287:287) (289:289:289))
        (IOPATH datab combout (273:273:273) (275:275:275))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (921:921:921) (952:952:952))
        (PORT clk (1638:1638:1638) (1665:1665:1665))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2105:2105:2105) (2124:2124:2124))
        (PORT d[1] (1549:1549:1549) (1633:1633:1633))
        (PORT d[2] (1717:1717:1717) (1764:1764:1764))
        (PORT d[3] (1519:1519:1519) (1579:1579:1579))
        (PORT d[4] (1423:1423:1423) (1455:1455:1455))
        (PORT d[5] (2199:2199:2199) (2259:2259:2259))
        (PORT d[6] (2820:2820:2820) (2878:2878:2878))
        (PORT d[7] (2364:2364:2364) (2383:2383:2383))
        (PORT d[8] (1564:1564:1564) (1566:1566:1566))
        (PORT d[9] (1537:1537:1537) (1570:1570:1570))
        (PORT d[10] (1410:1410:1410) (1418:1418:1418))
        (PORT d[11] (1415:1415:1415) (1439:1439:1439))
        (PORT d[12] (2661:2661:2661) (2709:2709:2709))
        (PORT clk (1635:1635:1635) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1645:1645:1645) (1621:1621:1621))
        (PORT clk (1635:1635:1635) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1665:1665:1665))
        (PORT d[0] (2109:2109:2109) (2081:2081:2081))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1638:1638:1638) (1645:1645:1645))
        (PORT d[1] (1137:1137:1137) (1150:1150:1150))
        (PORT d[2] (1188:1188:1188) (1215:1215:1215))
        (PORT d[3] (1492:1492:1492) (1579:1579:1579))
        (PORT d[4] (2433:2433:2433) (2474:2474:2474))
        (PORT d[5] (2075:2075:2075) (2086:2086:2086))
        (PORT d[6] (2410:2410:2410) (2452:2452:2452))
        (PORT d[7] (1335:1335:1335) (1301:1301:1301))
        (PORT d[8] (1036:1036:1036) (1009:1009:1009))
        (PORT d[9] (1901:1901:1901) (1947:1947:1947))
        (PORT d[10] (1353:1353:1353) (1363:1363:1363))
        (PORT d[11] (2620:2620:2620) (2655:2655:2655))
        (PORT d[12] (2632:2632:2632) (2656:2656:2656))
        (PORT clk (1602:1602:1602) (1599:1599:1599))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1599:1599:1599))
        (PORT d[0] (700:700:700) (642:642:642))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1600:1600:1600))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1600:1600:1600))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1600:1600:1600))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[4\]\~12)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1157:1157:1157) (1222:1222:1222))
        (PORT datab (945:945:945) (1005:1005:1005))
        (PORT datac (1262:1262:1262) (1238:1238:1238))
        (PORT datad (1026:1026:1026) (996:996:996))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH datab combout (308:308:308) (281:281:281))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (918:918:918) (943:943:943))
        (PORT clk (1640:1640:1640) (1668:1668:1668))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2091:2091:2091) (2117:2117:2117))
        (PORT d[1] (1508:1508:1508) (1572:1572:1572))
        (PORT d[2] (1728:1728:1728) (1787:1787:1787))
        (PORT d[3] (1266:1266:1266) (1335:1335:1335))
        (PORT d[4] (1416:1416:1416) (1436:1436:1436))
        (PORT d[5] (2207:2207:2207) (2297:2297:2297))
        (PORT d[6] (1889:1889:1889) (1955:1955:1955))
        (PORT d[7] (2205:2205:2205) (2253:2253:2253))
        (PORT d[8] (1584:1584:1584) (1575:1575:1575))
        (PORT d[9] (1526:1526:1526) (1560:1560:1560))
        (PORT d[10] (1934:1934:1934) (1952:1952:1952))
        (PORT d[11] (1403:1403:1403) (1406:1406:1406))
        (PORT d[12] (2371:2371:2371) (2431:2431:2431))
        (PORT clk (1637:1637:1637) (1666:1666:1666))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1589:1589:1589) (1525:1525:1525))
        (PORT clk (1637:1637:1637) (1666:1666:1666))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1668:1668:1668))
        (PORT d[0] (2045:2045:2045) (1991:1991:1991))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1641:1641:1641) (1669:1669:1669))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1641:1641:1641) (1669:1669:1669))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1641:1641:1641) (1669:1669:1669))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1641:1641:1641) (1669:1669:1669))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1646:1646:1646) (1667:1667:1667))
        (PORT d[1] (1365:1365:1365) (1385:1385:1385))
        (PORT d[2] (1187:1187:1187) (1214:1214:1214))
        (PORT d[3] (911:911:911) (956:956:956))
        (PORT d[4] (2452:2452:2452) (2495:2495:2495))
        (PORT d[5] (2075:2075:2075) (2085:2085:2085))
        (PORT d[6] (2384:2384:2384) (2423:2423:2423))
        (PORT d[7] (808:808:808) (798:798:798))
        (PORT d[8] (1387:1387:1387) (1376:1376:1376))
        (PORT d[9] (2169:2169:2169) (2199:2199:2199))
        (PORT d[10] (1327:1327:1327) (1333:1333:1333))
        (PORT d[11] (2332:2332:2332) (2326:2326:2326))
        (PORT d[12] (2156:2156:2156) (2182:2182:2182))
        (PORT clk (1604:1604:1604) (1602:1602:1602))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1604:1604:1604) (1602:1602:1602))
        (PORT d[0] (500:500:500) (456:456:456))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1605:1605:1605) (1603:1603:1603))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1605:1605:1605) (1603:1603:1603))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1605:1605:1605) (1603:1603:1603))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1215:1215:1215) (1229:1229:1229))
        (PORT clk (1643:1643:1643) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1363:1363:1363) (1398:1398:1398))
        (PORT d[1] (1493:1493:1493) (1554:1554:1554))
        (PORT d[2] (1740:1740:1740) (1794:1794:1794))
        (PORT d[3] (1465:1465:1465) (1526:1526:1526))
        (PORT d[4] (1633:1633:1633) (1669:1669:1669))
        (PORT d[5] (2686:2686:2686) (2743:2743:2743))
        (PORT d[6] (3349:3349:3349) (3393:3393:3393))
        (PORT d[7] (2242:2242:2242) (2284:2284:2284))
        (PORT d[8] (1330:1330:1330) (1335:1335:1335))
        (PORT d[9] (1243:1243:1243) (1267:1267:1267))
        (PORT d[10] (1672:1672:1672) (1699:1699:1699))
        (PORT d[11] (1687:1687:1687) (1709:1709:1709))
        (PORT d[12] (2107:2107:2107) (2170:2170:2170))
        (PORT clk (1640:1640:1640) (1668:1668:1668))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1378:1378:1378) (1335:1335:1335))
        (PORT clk (1640:1640:1640) (1668:1668:1668))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1670:1670:1670))
        (PORT d[0] (1834:1834:1834) (1801:1801:1801))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1940:1940:1940) (1945:1945:1945))
        (PORT d[1] (1370:1370:1370) (1406:1406:1406))
        (PORT d[2] (1062:1062:1062) (1077:1077:1077))
        (PORT d[3] (865:865:865) (911:911:911))
        (PORT d[4] (2426:2426:2426) (2466:2466:2466))
        (PORT d[5] (2092:2092:2092) (2102:2102:2102))
        (PORT d[6] (2379:2379:2379) (2415:2415:2415))
        (PORT d[7] (1903:1903:1903) (1925:1925:1925))
        (PORT d[8] (1369:1369:1369) (1369:1369:1369))
        (PORT d[9] (1897:1897:1897) (1941:1941:1941))
        (PORT d[10] (1347:1347:1347) (1355:1355:1355))
        (PORT d[11] (2364:2364:2364) (2394:2394:2394))
        (PORT d[12] (1904:1904:1904) (1935:1935:1935))
        (PORT clk (1607:1607:1607) (1604:1604:1604))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1607:1607:1607) (1604:1604:1604))
        (PORT d[0] (725:725:725) (676:676:676))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1608:1608:1608) (1605:1605:1605))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1608:1608:1608) (1605:1605:1605))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1608:1608:1608) (1605:1605:1605))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[4\]\~11)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1153:1153:1153) (1216:1216:1216))
        (PORT datab (948:948:948) (1003:1003:1003))
        (PORT datac (1272:1272:1272) (1223:1223:1223))
        (PORT datad (1292:1292:1292) (1246:1246:1246))
        (IOPATH dataa combout (299:299:299) (304:304:304))
        (IOPATH datab combout (300:300:300) (312:312:312))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[4\]\~13)
    (DELAY
      (ABSOLUTE
        (PORT dataa (184:184:184) (221:221:221))
        (PORT datab (184:184:184) (218:218:218))
        (PORT datac (1065:1065:1065) (1090:1090:1090))
        (PORT datad (1026:1026:1026) (1010:1010:1010))
        (IOPATH dataa combout (272:272:272) (269:269:269))
        (IOPATH datab combout (273:273:273) (275:275:275))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1938:1938:1938) (1954:1954:1954))
        (PORT clk (1635:1635:1635) (1662:1662:1662))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2073:2073:2073) (2127:2127:2127))
        (PORT d[1] (1889:1889:1889) (2027:2027:2027))
        (PORT d[2] (2183:2183:2183) (2237:2237:2237))
        (PORT d[3] (1489:1489:1489) (1551:1551:1551))
        (PORT d[4] (1600:1600:1600) (1615:1615:1615))
        (PORT d[5] (1644:1644:1644) (1698:1698:1698))
        (PORT d[6] (1598:1598:1598) (1667:1667:1667))
        (PORT d[7] (1600:1600:1600) (1591:1591:1591))
        (PORT d[8] (1371:1371:1371) (1411:1411:1411))
        (PORT d[9] (1775:1775:1775) (1779:1779:1779))
        (PORT d[10] (1634:1634:1634) (1651:1651:1651))
        (PORT d[11] (2298:2298:2298) (2279:2279:2279))
        (PORT d[12] (2127:2127:2127) (2212:2212:2212))
        (PORT clk (1632:1632:1632) (1660:1660:1660))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1787:1787:1787) (1709:1709:1709))
        (PORT clk (1632:1632:1632) (1660:1660:1660))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1662:1662:1662))
        (PORT d[0] (2243:2243:2243) (2175:2175:2175))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1663:1663:1663))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1726:1726:1726) (1770:1770:1770))
        (PORT d[1] (2017:2017:2017) (2082:2082:2082))
        (PORT d[2] (1922:1922:1922) (1951:1951:1951))
        (PORT d[3] (1497:1497:1497) (1564:1564:1564))
        (PORT d[4] (2479:2479:2479) (2508:2508:2508))
        (PORT d[5] (2420:2420:2420) (2451:2451:2451))
        (PORT d[6] (2370:2370:2370) (2397:2397:2397))
        (PORT d[7] (1376:1376:1376) (1327:1327:1327))
        (PORT d[8] (2886:2886:2886) (2925:2925:2925))
        (PORT d[9] (2522:2522:2522) (2572:2572:2572))
        (PORT d[10] (3083:3083:3083) (3056:3056:3056))
        (PORT d[11] (2156:2156:2156) (2190:2190:2190))
        (PORT d[12] (1118:1118:1118) (1110:1110:1110))
        (PORT clk (1599:1599:1599) (1596:1596:1596))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1599:1599:1599) (1596:1596:1596))
        (PORT d[0] (1816:1816:1816) (1821:1821:1821))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1600:1600:1600) (1597:1597:1597))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1600:1600:1600) (1597:1597:1597))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1600:1600:1600) (1597:1597:1597))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1670:1670:1670) (1691:1691:1691))
        (PORT clk (1632:1632:1632) (1660:1660:1660))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2399:2399:2399) (2460:2460:2460))
        (PORT d[1] (1861:1861:1861) (1996:1996:1996))
        (PORT d[2] (2181:2181:2181) (2240:2240:2240))
        (PORT d[3] (1758:1758:1758) (1812:1812:1812))
        (PORT d[4] (1627:1627:1627) (1650:1650:1650))
        (PORT d[5] (1649:1649:1649) (1700:1700:1700))
        (PORT d[6] (2343:2343:2343) (2447:2447:2447))
        (PORT d[7] (1839:1839:1839) (1803:1803:1803))
        (PORT d[8] (1594:1594:1594) (1616:1616:1616))
        (PORT d[9] (1801:1801:1801) (1804:1804:1804))
        (PORT d[10] (1643:1643:1643) (1668:1668:1668))
        (PORT d[11] (2041:2041:2041) (2022:2022:2022))
        (PORT d[12] (2167:2167:2167) (2255:2255:2255))
        (PORT clk (1629:1629:1629) (1658:1658:1658))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2023:2023:2023) (1993:1993:1993))
        (PORT clk (1629:1629:1629) (1658:1658:1658))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1632:1632:1632) (1660:1660:1660))
        (PORT d[0] (2479:2479:2479) (2459:2459:2459))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1633:1633:1633) (1661:1661:1661))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1633:1633:1633) (1661:1661:1661))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1633:1633:1633) (1661:1661:1661))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1633:1633:1633) (1661:1661:1661))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1713:1713:1713) (1757:1757:1757))
        (PORT d[1] (1768:1768:1768) (1846:1846:1846))
        (PORT d[2] (1939:1939:1939) (1965:1965:1965))
        (PORT d[3] (1507:1507:1507) (1570:1570:1570))
        (PORT d[4] (2757:2757:2757) (2779:2779:2779))
        (PORT d[5] (2670:2670:2670) (2691:2691:2691))
        (PORT d[6] (2368:2368:2368) (2395:2395:2395))
        (PORT d[7] (905:905:905) (907:907:907))
        (PORT d[8] (2874:2874:2874) (2921:2921:2921))
        (PORT d[9] (2514:2514:2514) (2564:2564:2564))
        (PORT d[10] (2817:2817:2817) (2802:2802:2802))
        (PORT d[11] (2434:2434:2434) (2466:2466:2466))
        (PORT d[12] (884:884:884) (883:883:883))
        (PORT clk (1596:1596:1596) (1594:1594:1594))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1596:1596:1596) (1594:1594:1594))
        (PORT d[0] (1207:1207:1207) (1171:1171:1171))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1597:1597:1597) (1595:1595:1595))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1597:1597:1597) (1595:1595:1595))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1597:1597:1597) (1595:1595:1595))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[3\]\~14)
    (DELAY
      (ABSOLUTE
        (PORT dataa (823:823:823) (791:791:791))
        (PORT datab (949:949:949) (1004:1004:1004))
        (PORT datac (569:569:569) (569:569:569))
        (PORT datad (1127:1127:1127) (1176:1176:1176))
        (IOPATH dataa combout (273:273:273) (269:269:269))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1436:1436:1436) (1469:1469:1469))
        (PORT clk (1626:1626:1626) (1655:1655:1655))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2103:2103:2103) (2168:2168:2168))
        (PORT d[1] (1824:1824:1824) (1940:1940:1940))
        (PORT d[2] (1683:1683:1683) (1741:1741:1741))
        (PORT d[3] (1790:1790:1790) (1852:1852:1852))
        (PORT d[4] (1859:1859:1859) (1879:1879:1879))
        (PORT d[5] (1646:1646:1646) (1675:1675:1675))
        (PORT d[6] (2063:2063:2063) (2168:2168:2168))
        (PORT d[7] (1875:1875:1875) (1882:1882:1882))
        (PORT d[8] (1628:1628:1628) (1663:1663:1663))
        (PORT d[9] (1824:1824:1824) (1819:1819:1819))
        (PORT d[10] (1647:1647:1647) (1674:1674:1674))
        (PORT d[11] (1551:1551:1551) (1558:1558:1558))
        (PORT d[12] (1876:1876:1876) (1951:1951:1951))
        (PORT clk (1623:1623:1623) (1653:1653:1653))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1790:1790:1790) (1809:1809:1809))
        (PORT clk (1623:1623:1623) (1653:1653:1653))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1626:1626:1626) (1655:1655:1655))
        (PORT d[0] (2246:2246:2246) (2275:2275:2275))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1627:1627:1627) (1656:1656:1656))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1627:1627:1627) (1656:1656:1656))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1627:1627:1627) (1656:1656:1656))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1627:1627:1627) (1656:1656:1656))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1395:1395:1395) (1424:1424:1424))
        (PORT d[1] (1423:1423:1423) (1426:1426:1426))
        (PORT d[2] (1456:1456:1456) (1485:1485:1485))
        (PORT d[3] (1420:1420:1420) (1470:1470:1470))
        (PORT d[4] (2747:2747:2747) (2787:2787:2787))
        (PORT d[5] (2685:2685:2685) (2712:2712:2712))
        (PORT d[6] (2404:2404:2404) (2441:2441:2441))
        (PORT d[7] (1129:1129:1129) (1098:1098:1098))
        (PORT d[8] (2878:2878:2878) (2928:2928:2928))
        (PORT d[9] (2761:2761:2761) (2793:2793:2793))
        (PORT d[10] (2803:2803:2803) (2804:2804:2804))
        (PORT d[11] (2446:2446:2446) (2487:2487:2487))
        (PORT d[12] (1089:1089:1089) (1082:1082:1082))
        (PORT clk (1590:1590:1590) (1589:1589:1589))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1590:1590:1590) (1589:1589:1589))
        (PORT d[0] (981:981:981) (928:928:928))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1591:1591:1591) (1590:1590:1590))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1591:1591:1591) (1590:1590:1590))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1591:1591:1591) (1590:1590:1590))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[3\]\~15)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1157:1157:1157) (1229:1229:1229))
        (PORT datab (945:945:945) (1002:1002:1002))
        (PORT datac (769:769:769) (760:760:760))
        (PORT datad (998:998:998) (967:967:967))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH datab combout (308:308:308) (281:281:281))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[3\]\~16)
    (DELAY
      (ABSOLUTE
        (PORT dataa (358:358:358) (367:367:367))
        (PORT datab (182:182:182) (214:214:214))
        (PORT datac (1068:1068:1068) (1093:1093:1093))
        (PORT datad (1024:1024:1024) (1010:1010:1010))
        (IOPATH dataa combout (272:272:272) (269:269:269))
        (IOPATH datab combout (273:273:273) (275:275:275))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1175:1175:1175) (1210:1210:1210))
        (PORT clk (1646:1646:1646) (1674:1674:1674))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2179:2179:2179) (2206:2206:2206))
        (PORT d[1] (959:959:959) (1008:1008:1008))
        (PORT d[2] (1498:1498:1498) (1555:1555:1555))
        (PORT d[3] (972:972:972) (1029:1029:1029))
        (PORT d[4] (933:933:933) (961:961:961))
        (PORT d[5] (911:911:911) (923:923:923))
        (PORT d[6] (2371:2371:2371) (2445:2445:2445))
        (PORT d[7] (2564:2564:2564) (2632:2632:2632))
        (PORT d[8] (2120:2120:2120) (2122:2122:2122))
        (PORT d[9] (954:954:954) (970:970:970))
        (PORT d[10] (1966:1966:1966) (2001:2001:2001))
        (PORT d[11] (1432:1432:1432) (1470:1470:1470))
        (PORT d[12] (870:870:870) (873:873:873))
        (PORT clk (1643:1643:1643) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1125:1125:1125) (1080:1080:1080))
        (PORT clk (1643:1643:1643) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1674:1674:1674))
        (PORT d[0] (1581:1581:1581) (1546:1546:1546))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1458:1458:1458) (1494:1494:1494))
        (PORT d[1] (1894:1894:1894) (1924:1924:1924))
        (PORT d[2] (1236:1236:1236) (1259:1259:1259))
        (PORT d[3] (904:904:904) (966:966:966))
        (PORT d[4] (2170:2170:2170) (2202:2202:2202))
        (PORT d[5] (1604:1604:1604) (1583:1583:1583))
        (PORT d[6] (1851:1851:1851) (1870:1870:1870))
        (PORT d[7] (1613:1613:1613) (1632:1632:1632))
        (PORT d[8] (1896:1896:1896) (1926:1926:1926))
        (PORT d[9] (1620:1620:1620) (1647:1647:1647))
        (PORT d[10] (1592:1592:1592) (1571:1571:1571))
        (PORT d[11] (2090:2090:2090) (2109:2109:2109))
        (PORT d[12] (1882:1882:1882) (1895:1895:1895))
        (PORT clk (1610:1610:1610) (1608:1608:1608))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1608:1608:1608))
        (PORT d[0] (998:998:998) (969:969:969))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1609:1609:1609))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1609:1609:1609))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1609:1609:1609))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[2\]\~18)
    (DELAY
      (ABSOLUTE
        (PORT dataa (921:921:921) (989:989:989))
        (PORT datab (1075:1075:1075) (1066:1066:1066))
        (PORT datac (912:912:912) (990:990:990))
        (PORT datad (811:811:811) (782:782:782))
        (IOPATH dataa combout (290:290:290) (306:306:306))
        (IOPATH datab combout (295:295:295) (300:300:300))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1169:1169:1169) (1216:1216:1216))
        (PORT clk (1646:1646:1646) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2190:2190:2190) (2216:2216:2216))
        (PORT d[1] (1258:1258:1258) (1322:1322:1322))
        (PORT d[2] (1194:1194:1194) (1215:1215:1215))
        (PORT d[3] (694:694:694) (733:733:733))
        (PORT d[4] (660:660:660) (664:664:664))
        (PORT d[5] (636:636:636) (639:639:639))
        (PORT d[6] (632:632:632) (636:636:636))
        (PORT d[7] (645:645:645) (643:643:643))
        (PORT d[8] (613:613:613) (611:611:611))
        (PORT d[9] (1500:1500:1500) (1531:1531:1531))
        (PORT d[10] (674:674:674) (671:671:671))
        (PORT d[11] (1688:1688:1688) (1717:1717:1717))
        (PORT d[12] (643:643:643) (646:646:646))
        (PORT clk (1643:1643:1643) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (865:865:865) (804:804:804))
        (PORT clk (1643:1643:1643) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1672:1672:1672))
        (PORT d[0] (1321:1321:1321) (1270:1270:1270))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1687:1687:1687) (1702:1702:1702))
        (PORT d[1] (1657:1657:1657) (1692:1692:1692))
        (PORT d[2] (1475:1475:1475) (1498:1498:1498))
        (PORT d[3] (1164:1164:1164) (1238:1238:1238))
        (PORT d[4] (1889:1889:1889) (1908:1908:1908))
        (PORT d[5] (1841:1841:1841) (1838:1838:1838))
        (PORT d[6] (1318:1318:1318) (1303:1303:1303))
        (PORT d[7] (1588:1588:1588) (1587:1587:1587))
        (PORT d[8] (1872:1872:1872) (1886:1886:1886))
        (PORT d[9] (1849:1849:1849) (1869:1869:1869))
        (PORT d[10] (1647:1647:1647) (1639:1639:1639))
        (PORT d[11] (1787:1787:1787) (1770:1770:1770))
        (PORT d[12] (1347:1347:1347) (1347:1347:1347))
        (PORT clk (1610:1610:1610) (1606:1606:1606))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1606:1606:1606))
        (PORT d[0] (1012:1012:1012) (981:981:981))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1607:1607:1607))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1607:1607:1607))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1607:1607:1607))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1424:1424:1424) (1469:1469:1469))
        (PORT clk (1644:1644:1644) (1671:1671:1671))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2157:2157:2157) (2194:2194:2194))
        (PORT d[1] (918:918:918) (940:940:940))
        (PORT d[2] (938:938:938) (975:975:975))
        (PORT d[3] (1210:1210:1210) (1233:1233:1233))
        (PORT d[4] (921:921:921) (932:932:932))
        (PORT d[5] (896:896:896) (903:903:903))
        (PORT d[6] (914:914:914) (915:915:915))
        (PORT d[7] (2811:2811:2811) (2884:2884:2884))
        (PORT d[8] (2412:2412:2412) (2417:2417:2417))
        (PORT d[9] (944:944:944) (953:953:953))
        (PORT d[10] (914:914:914) (924:924:924))
        (PORT d[11] (1723:1723:1723) (1763:1763:1763))
        (PORT d[12] (935:935:935) (943:943:943))
        (PORT clk (1641:1641:1641) (1669:1669:1669))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1376:1376:1376) (1305:1305:1305))
        (PORT clk (1641:1641:1641) (1669:1669:1669))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (PORT d[0] (1832:1832:1832) (1771:1771:1771))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1672:1672:1672))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1672:1672:1672))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1672:1672:1672))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1672:1672:1672))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1457:1457:1457) (1492:1492:1492))
        (PORT d[1] (1127:1127:1127) (1179:1179:1179))
        (PORT d[2] (1487:1487:1487) (1529:1529:1529))
        (PORT d[3] (1138:1138:1138) (1196:1196:1196))
        (PORT d[4] (1622:1622:1622) (1619:1619:1619))
        (PORT d[5] (1649:1649:1649) (1647:1647:1647))
        (PORT d[6] (1540:1540:1540) (1541:1541:1541))
        (PORT d[7] (1625:1625:1625) (1633:1633:1633))
        (PORT d[8] (1847:1847:1847) (1836:1836:1836))
        (PORT d[9] (1575:1575:1575) (1576:1576:1576))
        (PORT d[10] (1585:1585:1585) (1591:1591:1591))
        (PORT d[11] (1542:1542:1542) (1544:1544:1544))
        (PORT d[12] (1596:1596:1596) (1594:1594:1594))
        (PORT clk (1608:1608:1608) (1605:1605:1605))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1608:1608:1608) (1605:1605:1605))
        (PORT d[0] (1552:1552:1552) (1540:1540:1540))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1609:1609:1609) (1606:1606:1606))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1609:1609:1609) (1606:1606:1606))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1609:1609:1609) (1606:1606:1606))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[2\]\~17)
    (DELAY
      (ABSOLUTE
        (PORT dataa (927:927:927) (996:996:996))
        (PORT datab (1093:1093:1093) (1046:1046:1046))
        (PORT datac (917:917:917) (998:998:998))
        (PORT datad (1319:1319:1319) (1308:1308:1308))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[2\]\~19)
    (DELAY
      (ABSOLUTE
        (PORT dataa (842:842:842) (875:875:875))
        (PORT datab (685:685:685) (763:763:763))
        (PORT datac (157:157:157) (188:188:188))
        (PORT datad (159:159:159) (180:180:180))
        (IOPATH dataa combout (307:307:307) (280:280:280))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (917:917:917) (955:955:955))
        (PORT clk (1646:1646:1646) (1673:1673:1673))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1078:1078:1078) (1101:1101:1101))
        (PORT d[1] (1781:1781:1781) (1841:1841:1841))
        (PORT d[2] (1485:1485:1485) (1545:1545:1545))
        (PORT d[3] (1220:1220:1220) (1270:1270:1270))
        (PORT d[4] (1162:1162:1162) (1178:1178:1178))
        (PORT d[5] (939:939:939) (956:956:956))
        (PORT d[6] (2137:2137:2137) (2211:2211:2211))
        (PORT d[7] (2232:2232:2232) (2284:2284:2284))
        (PORT d[8] (1811:1811:1811) (1788:1788:1788))
        (PORT d[9] (944:944:944) (957:957:957))
        (PORT d[10] (1961:1961:1961) (1986:1986:1986))
        (PORT d[11] (1442:1442:1442) (1464:1464:1464))
        (PORT d[12] (2404:2404:2404) (2478:2478:2478))
        (PORT clk (1643:1643:1643) (1671:1671:1671))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1338:1338:1338) (1274:1274:1274))
        (PORT clk (1643:1643:1643) (1671:1671:1671))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (PORT d[0] (1794:1794:1794) (1740:1740:1740))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1477:1477:1477) (1514:1514:1514))
        (PORT d[1] (1668:1668:1668) (1698:1698:1698))
        (PORT d[2] (1186:1186:1186) (1203:1203:1203))
        (PORT d[3] (1149:1149:1149) (1163:1163:1163))
        (PORT d[4] (2183:2183:2183) (2216:2216:2216))
        (PORT d[5] (1777:1777:1777) (1766:1766:1766))
        (PORT d[6] (2120:2120:2120) (2145:2145:2145))
        (PORT d[7] (1649:1649:1649) (1679:1679:1679))
        (PORT d[8] (1661:1661:1661) (1683:1683:1683))
        (PORT d[9] (1633:1633:1633) (1670:1670:1670))
        (PORT d[10] (1381:1381:1381) (1374:1374:1374))
        (PORT d[11] (2075:2075:2075) (2049:2049:2049))
        (PORT d[12] (1637:1637:1637) (1669:1669:1669))
        (PORT clk (1610:1610:1610) (1607:1607:1607))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1607:1607:1607))
        (PORT d[0] (1005:1005:1005) (963:963:963))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1608:1608:1608))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1608:1608:1608))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1608:1608:1608))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (970:970:970) (1011:1011:1011))
        (PORT clk (1645:1645:1645) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1645:1645:1645) (1656:1656:1656))
        (PORT d[1] (1751:1751:1751) (1815:1815:1815))
        (PORT d[2] (1473:1473:1473) (1522:1522:1522))
        (PORT d[3] (1254:1254:1254) (1312:1312:1312))
        (PORT d[4] (1636:1636:1636) (1674:1674:1674))
        (PORT d[5] (2421:2421:2421) (2491:2491:2491))
        (PORT d[6] (2111:2111:2111) (2182:2182:2182))
        (PORT d[7] (2257:2257:2257) (2312:2312:2312))
        (PORT d[8] (1821:1821:1821) (1798:1798:1798))
        (PORT d[9] (1255:1255:1255) (1283:1283:1283))
        (PORT d[10] (1166:1166:1166) (1174:1174:1174))
        (PORT d[11] (1149:1149:1149) (1176:1176:1176))
        (PORT d[12] (2394:2394:2394) (2464:2464:2464))
        (PORT clk (1642:1642:1642) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1342:1342:1342) (1291:1291:1291))
        (PORT clk (1642:1642:1642) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1672:1672:1672))
        (PORT d[0] (1798:1798:1798) (1757:1757:1757))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (868:868:868) (869:869:869))
        (PORT d[1] (1391:1391:1391) (1421:1421:1421))
        (PORT d[2] (935:935:935) (948:948:948))
        (PORT d[3] (613:613:613) (649:649:649))
        (PORT d[4] (2152:2152:2152) (2186:2186:2186))
        (PORT d[5] (1792:1792:1792) (1777:1777:1777))
        (PORT d[6] (2099:2099:2099) (2123:2123:2123))
        (PORT d[7] (1650:1650:1650) (1680:1680:1680))
        (PORT d[8] (1661:1661:1661) (1684:1684:1684))
        (PORT d[9] (1634:1634:1634) (1671:1671:1671))
        (PORT d[10] (1565:1565:1565) (1525:1525:1525))
        (PORT d[11] (2334:2334:2334) (2359:2359:2359))
        (PORT d[12] (2166:2166:2166) (2195:2195:2195))
        (PORT clk (1609:1609:1609) (1606:1606:1606))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1609:1609:1609) (1606:1606:1606))
        (PORT d[0] (952:952:952) (908:908:908))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1607:1607:1607))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1607:1607:1607))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1607:1607:1607))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[1\]\~21)
    (DELAY
      (ABSOLUTE
        (PORT dataa (955:955:955) (1028:1028:1028))
        (PORT datab (1051:1051:1051) (1025:1025:1025))
        (PORT datac (896:896:896) (961:961:961))
        (PORT datad (1067:1067:1067) (1046:1046:1046))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH datab combout (319:319:319) (307:307:307))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (938:938:938) (984:984:984))
        (PORT clk (1646:1646:1646) (1674:1674:1674))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1885:1885:1885) (1913:1913:1913))
        (PORT d[1] (956:956:956) (1010:1010:1010))
        (PORT d[2] (1497:1497:1497) (1554:1554:1554))
        (PORT d[3] (1431:1431:1431) (1450:1450:1450))
        (PORT d[4] (917:917:917) (941:941:941))
        (PORT d[5] (1111:1111:1111) (1107:1107:1107))
        (PORT d[6] (1442:1442:1442) (1479:1479:1479))
        (PORT d[7] (2579:2579:2579) (2649:2649:2649))
        (PORT d[8] (1070:1070:1070) (1069:1069:1069))
        (PORT d[9] (943:943:943) (956:956:956))
        (PORT d[10] (1940:1940:1940) (1972:1972:1972))
        (PORT d[11] (1450:1450:1450) (1484:1484:1484))
        (PORT d[12] (2380:2380:2380) (2451:2451:2451))
        (PORT clk (1643:1643:1643) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1148:1148:1148) (1111:1111:1111))
        (PORT clk (1643:1643:1643) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1674:1674:1674))
        (PORT d[0] (1604:1604:1604) (1577:1577:1577))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1446:1446:1446) (1488:1488:1488))
        (PORT d[1] (1629:1629:1629) (1679:1679:1679))
        (PORT d[2] (1205:1205:1205) (1226:1226:1226))
        (PORT d[3] (1122:1122:1122) (1162:1162:1162))
        (PORT d[4] (2203:2203:2203) (2236:2236:2236))
        (PORT d[5] (1772:1772:1772) (1749:1749:1749))
        (PORT d[6] (2096:2096:2096) (2112:2112:2112))
        (PORT d[7] (1645:1645:1645) (1672:1672:1672))
        (PORT d[8] (1897:1897:1897) (1927:1927:1927))
        (PORT d[9] (1627:1627:1627) (1661:1661:1661))
        (PORT d[10] (1603:1603:1603) (1586:1586:1586))
        (PORT d[11] (2094:2094:2094) (2115:2115:2115))
        (PORT d[12] (1611:1611:1611) (1640:1640:1640))
        (PORT clk (1610:1610:1610) (1608:1608:1608))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1608:1608:1608))
        (PORT d[0] (930:930:930) (891:891:891))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1609:1609:1609))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1609:1609:1609))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1609:1609:1609))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[1\]\~20)
    (DELAY
      (ABSOLUTE
        (PORT dataa (925:925:925) (995:995:995))
        (PORT datab (1090:1090:1090) (1066:1066:1066))
        (PORT datac (917:917:917) (992:992:992))
        (PORT datad (1030:1030:1030) (986:986:986))
        (IOPATH dataa combout (290:290:290) (306:306:306))
        (IOPATH datab combout (295:295:295) (300:300:300))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[1\]\~22)
    (DELAY
      (ABSOLUTE
        (PORT dataa (842:842:842) (875:875:875))
        (PORT datab (685:685:685) (763:763:763))
        (PORT datac (156:156:156) (187:187:187))
        (PORT datad (159:159:159) (180:180:180))
        (IOPATH dataa combout (309:309:309) (326:326:326))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[1\]\~23)
    (DELAY
      (ABSOLUTE
        (PORT dataa (184:184:184) (221:221:221))
        (PORT datab (685:685:685) (762:762:762))
        (PORT datac (1010:1010:1010) (1039:1039:1039))
        (PORT datad (650:650:650) (696:696:696))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH datab combout (319:319:319) (307:307:307))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1237:1237:1237) (1296:1296:1296))
        (PORT clk (1646:1646:1646) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1898:1898:1898) (1926:1926:1926))
        (PORT d[1] (1245:1245:1245) (1310:1310:1310))
        (PORT d[2] (1222:1222:1222) (1255:1255:1255))
        (PORT d[3] (983:983:983) (1025:1025:1025))
        (PORT d[4] (902:902:902) (909:909:909))
        (PORT d[5] (927:927:927) (928:928:928))
        (PORT d[6] (2376:2376:2376) (2455:2455:2455))
        (PORT d[7] (2548:2548:2548) (2616:2616:2616))
        (PORT d[8] (2104:2104:2104) (2106:2106:2106))
        (PORT d[9] (918:918:918) (914:914:914))
        (PORT d[10] (910:910:910) (909:909:909))
        (PORT d[11] (1461:1461:1461) (1504:1504:1504))
        (PORT d[12] (2683:2683:2683) (2765:2765:2765))
        (PORT clk (1643:1643:1643) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (890:890:890) (828:828:828))
        (PORT clk (1643:1643:1643) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1672:1672:1672))
        (PORT d[0] (1346:1346:1346) (1294:1294:1294))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1199:1199:1199) (1220:1220:1220))
        (PORT d[1] (1644:1644:1644) (1688:1688:1688))
        (PORT d[2] (1208:1208:1208) (1244:1244:1244))
        (PORT d[3] (892:892:892) (952:952:952))
        (PORT d[4] (1870:1870:1870) (1887:1887:1887))
        (PORT d[5] (1353:1353:1353) (1350:1350:1350))
        (PORT d[6] (1822:1822:1822) (1836:1836:1836))
        (PORT d[7] (1333:1333:1333) (1345:1345:1345))
        (PORT d[8] (1342:1342:1342) (1339:1339:1339))
        (PORT d[9] (1365:1365:1365) (1368:1368:1368))
        (PORT d[10] (1328:1328:1328) (1330:1330:1330))
        (PORT d[11] (1544:1544:1544) (1525:1525:1525))
        (PORT d[12] (1622:1622:1622) (1637:1637:1637))
        (PORT clk (1610:1610:1610) (1606:1606:1606))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1606:1606:1606))
        (PORT d[0] (1192:1192:1192) (1159:1159:1159))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1607:1607:1607))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1607:1607:1607))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1607:1607:1607))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[0\]\~24)
    (DELAY
      (ABSOLUTE
        (PORT dataa (950:950:950) (1027:1027:1027))
        (PORT datab (1078:1078:1078) (1066:1066:1066))
        (PORT datac (892:892:892) (957:957:957))
        (PORT datad (1037:1037:1037) (1007:1007:1007))
        (IOPATH dataa combout (290:290:290) (306:306:306))
        (IOPATH datab combout (295:295:295) (300:300:300))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1581:1581:1581) (1676:1676:1676))
        (PORT clk (1638:1638:1638) (1665:1665:1665))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2028:2028:2028) (2073:2073:2073))
        (PORT d[1] (2428:2428:2428) (2581:2581:2581))
        (PORT d[2] (2772:2772:2772) (2846:2846:2846))
        (PORT d[3] (943:943:943) (976:976:976))
        (PORT d[4] (1045:1045:1045) (1003:1003:1003))
        (PORT d[5] (799:799:799) (803:803:803))
        (PORT d[6] (1499:1499:1499) (1545:1545:1545))
        (PORT d[7] (789:789:789) (781:781:781))
        (PORT d[8] (810:810:810) (816:816:816))
        (PORT d[9] (778:778:778) (768:768:768))
        (PORT d[10] (846:846:846) (837:837:837))
        (PORT d[11] (2629:2629:2629) (2644:2644:2644))
        (PORT d[12] (1811:1811:1811) (1819:1819:1819))
        (PORT clk (1635:1635:1635) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2336:2336:2336) (2286:2286:2286))
        (PORT clk (1635:1635:1635) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1665:1665:1665))
        (PORT d[0] (2792:2792:2792) (2752:2752:2752))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1660:1660:1660) (1678:1678:1678))
        (PORT d[1] (1444:1444:1444) (1496:1496:1496))
        (PORT d[2] (1716:1716:1716) (1775:1775:1775))
        (PORT d[3] (1747:1747:1747) (1806:1806:1806))
        (PORT d[4] (1627:1627:1627) (1647:1647:1647))
        (PORT d[5] (1805:1805:1805) (1809:1809:1809))
        (PORT d[6] (2012:2012:2012) (1989:1989:1989))
        (PORT d[7] (1905:1905:1905) (1931:1931:1931))
        (PORT d[8] (2301:2301:2301) (2313:2313:2313))
        (PORT d[9] (1862:1862:1862) (1866:1866:1866))
        (PORT d[10] (1958:1958:1958) (1931:1931:1931))
        (PORT d[11] (1877:1877:1877) (1881:1881:1881))
        (PORT d[12] (1883:1883:1883) (1912:1912:1912))
        (PORT clk (1602:1602:1602) (1599:1599:1599))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1599:1599:1599))
        (PORT d[0] (1241:1241:1241) (1231:1231:1231))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1600:1600:1600))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1600:1600:1600))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1600:1600:1600))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1464:1464:1464) (1516:1516:1516))
        (PORT clk (1646:1646:1646) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2155:2155:2155) (2188:2188:2188))
        (PORT d[1] (1239:1239:1239) (1301:1301:1301))
        (PORT d[2] (954:954:954) (976:976:976))
        (PORT d[3] (927:927:927) (942:942:942))
        (PORT d[4] (904:904:904) (905:905:905))
        (PORT d[5] (914:914:914) (902:902:902))
        (PORT d[6] (879:879:879) (866:866:866))
        (PORT d[7] (2851:2851:2851) (2926:2926:2926))
        (PORT d[8] (2387:2387:2387) (2382:2382:2382))
        (PORT d[9] (932:932:932) (934:934:934))
        (PORT d[10] (900:900:900) (894:894:894))
        (PORT d[11] (1718:1718:1718) (1759:1759:1759))
        (PORT d[12] (918:918:918) (922:922:922))
        (PORT clk (1643:1643:1643) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1551:1551:1551) (1449:1449:1449))
        (PORT clk (1643:1643:1643) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1672:1672:1672))
        (PORT d[0] (2007:2007:2007) (1915:1915:1915))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1465:1465:1465) (1503:1503:1503))
        (PORT d[1] (1383:1383:1383) (1414:1414:1414))
        (PORT d[2] (1484:1484:1484) (1516:1516:1516))
        (PORT d[3] (1189:1189:1189) (1261:1261:1261))
        (PORT d[4] (1860:1860:1860) (1877:1877:1877))
        (PORT d[5] (1832:1832:1832) (1824:1824:1824))
        (PORT d[6] (1558:1558:1558) (1539:1539:1539))
        (PORT d[7] (1622:1622:1622) (1635:1635:1635))
        (PORT d[8] (1584:1584:1584) (1583:1583:1583))
        (PORT d[9] (1847:1847:1847) (1864:1864:1864))
        (PORT d[10] (1962:1962:1962) (1930:1930:1930))
        (PORT d[11] (1793:1793:1793) (1796:1796:1796))
        (PORT d[12] (1591:1591:1591) (1577:1577:1577))
        (PORT clk (1610:1610:1610) (1606:1606:1606))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1606:1606:1606))
        (PORT d[0] (1444:1444:1444) (1405:1405:1405))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1607:1607:1607))
        (IOPATH (posedge clk) pulse (0:0:0) (2229:2229:2229))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1607:1607:1607))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1607:1607:1607))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[0\]\~25)
    (DELAY
      (ABSOLUTE
        (PORT dataa (950:950:950) (1026:1026:1026))
        (PORT datab (1007:1007:1007) (981:981:981))
        (PORT datac (892:892:892) (956:956:956))
        (PORT datad (1033:1033:1033) (1017:1017:1017))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH datab combout (308:308:308) (281:281:281))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[0\]\~26)
    (DELAY
      (ABSOLUTE
        (PORT dataa (842:842:842) (875:875:875))
        (PORT datab (685:685:685) (761:761:761))
        (PORT datac (156:156:156) (187:187:187))
        (PORT datad (159:159:159) (180:180:180))
        (IOPATH dataa combout (309:309:309) (326:326:326))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[0\]\~27)
    (DELAY
      (ABSOLUTE
        (PORT dataa (845:845:845) (876:876:876))
        (PORT datab (690:690:690) (730:730:730))
        (PORT datac (1013:1013:1013) (1038:1038:1038))
        (PORT datad (159:159:159) (180:180:180))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
)
